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Groups > linux.kernel > #1711813
| From | Ding Tianhong <dingtianhong@huawei.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH v11 3/5] PCI: Disable Relaxed Ordering Attributes for AMD A1100 |
| Date | 2017-08-15 05:30 +0200 |
| Message-ID | <ueAIi-4oo-9@gated-at.bofh.it> (permalink) |
| References | <ueAIi-4oo-3@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
Casey reported that the AMD ARM A1100 SoC has a bug in its PCIe Root Port where Upstream Transaction Layer Packets with the Relaxed Ordering Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering set, it would cause Data Corruption, so we need to disable Relaxed Ordering Attribute when Upstream TLPs to the Root Port. Reported-and-suggested-by: Casey Leedom <leedom@chelsio.com> Signed-off-by: Casey Leedom <leedom@chelsio.com> Signed-off-by: Ding Tianhong <dingtianhong@huawei.com> Acked-by: Casey Leedom <leedom@chelsio.com> --- drivers/pci/quirks.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 1272f7e..1407604 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -4089,6 +4089,22 @@ static void quirk_relaxedordering_disable(struct pci_dev *dev) quirk_relaxedordering_disable); /* + * The AMD ARM A1100 (AKA "SEATTLE") SoC has a bug in its PCIe Root Complex + * where Upstream Transaction Layer Packets with the Relaxed Ordering + * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering + * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules + * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0 + * November 10, 2010). As a result, on this platform we can't use Relaxed + * Ordering for Upstream TLPs. + */ +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8, + quirk_relaxedordering_disable); +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8, + quirk_relaxedordering_disable); +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8, + quirk_relaxedordering_disable); + +/* * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same * values for the Attribute as were supplied in the header of the * corresponding Request, except as explicitly allowed when IDO is used." -- 1.8.3.1
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[PATCH v11 0/5] Add new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag Ding Tianhong <dingtianhong@huawei.com> - 2017-08-15 05:30 +0200
[PATCH v11 5/5] net/cxgb4vf: Use new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag Ding Tianhong <dingtianhong@huawei.com> - 2017-08-15 05:30 +0200
[PATCH v11 2/5] PCI: Disable Relaxed Ordering for some Intel processors Ding Tianhong <dingtianhong@huawei.com> - 2017-08-15 05:30 +0200
[PATCH v11 4/5] net/cxgb4: Use new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag Ding Tianhong <dingtianhong@huawei.com> - 2017-08-15 05:30 +0200
[PATCH v11 3/5] PCI: Disable Relaxed Ordering Attributes for AMD A1100 Ding Tianhong <dingtianhong@huawei.com> - 2017-08-15 05:30 +0200
Re: [PATCH v11 0/5] Add new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag David Miller <davem@davemloft.net> - 2017-08-15 07:20 +0200
Re: [PATCH v11 0/5] Add new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag Eric Dumazet <eric.dumazet@gmail.com> - 2017-08-15 16:00 +0200
Re: [PATCH v11 0/5] Add new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag Eric Dumazet <eric.dumazet@gmail.com> - 2017-08-15 16:10 +0200
Re: [PATCH v11 0/5] Add new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag Ding Tianhong <dingtianhong@huawei.com> - 2017-08-15 16:50 +0200
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