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Groups > linux.kernel > #1709681
| From | Icenowy Zheng <icenowy@aosc.io> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH 2/2] arm64: allwinner: h5: fix pinctrl IRQs |
| Date | 2017-08-11 16:30 +0200 |
| Message-ID | <udj6P-4Eb-41@gated-at.bofh.it> (permalink) |
| References | <udj6O-4Eb-15@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
The pin controller of H5 has three IRQs at the chip's GIC, which
represents three banks of pinctrl IRQs. However, the device tree used to
miss the third IRQ of the pin controller, which makes the PG bank IRQ
not usable.
Add the missing IRQ to the pinctrl node.
Fixes: 4e36de179f27 ("arm64: allwinner: h5: add Allwinner H5 .dtsi")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
index 732e2e06f503..d9a720bff05d 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
@@ -120,5 +120,8 @@
};
&pio {
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
compatible = "allwinner,sun50i-h5-pinctrl";
};
--
2.13.0
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[PATCH 0/2] Allwinner H5 IRQ fixes Icenowy Zheng <icenowy@aosc.io> - 2017-08-11 16:30 +0200
[PATCH 1/2] pinctrl: sunxi: fix wrong irq_banks number for H5 pinctrl Icenowy Zheng <icenowy@aosc.io> - 2017-08-11 16:30 +0200
Re: [linux-sunxi] [PATCH 1/2] pinctrl: sunxi: fix wrong irq_banks number for H5 pinctrl Chen-Yu Tsai <wens@csie.org> - 2017-08-14 08:10 +0200
Re: [PATCH 1/2] pinctrl: sunxi: fix wrong irq_banks number for H5 pinctrl Linus Walleij <linus.walleij@linaro.org> - 2017-08-22 14:50 +0200
[PATCH 2/2] arm64: allwinner: h5: fix pinctrl IRQs Icenowy Zheng <icenowy@aosc.io> - 2017-08-11 16:30 +0200
Re: [linux-sunxi] [PATCH 2/2] arm64: allwinner: h5: fix pinctrl IRQs Chen-Yu Tsai <wens@csie.org> - 2017-08-14 08:30 +0200
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