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Re: IRQ_ONESHOT expectations vs mask/unmask

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On Mon, 31 Jul 2017, Benjamin Herrenschmidt wrote:
> On Mon, 2017-07-31 at 09:09 +0200, Thomas Gleixner wrote:
> > You asked a lot of questions, but you failed to explain the problem for
> > XICS.
> 
> I did but maybe it wasn't clear :-)
> 
> "So on some PICs on powerpc, while we do use "fast EOI", we also> >
> have a chance of edge interrupts (MSIs) being lost while masked."
> 
> Basically, a masked interrupt might get dropped rather than "latched",
> so if we use the existing fasteoi handler with IRQF_ONESHOT, we'll
> lose them if they occur at the wrong time.
> 
> I could use something like the edge_eoi flow handler instead I suppose
> but that will *never* lazy disable which is somewhat unfortunate, very
> fast paced MSIs benefit from being HW masked if we already recorded
> that they occurred.
> 
> So what I would need is something along the line of ONESHOT as done in
> fasteoi but only for level interrupts.

If that MSI interrupt is using a separate interrupt chip, then the solution
is simple. You just have to add IRQCHIP_ONESHOT_SAFE to chip.flags

Thanks,

	tglx

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Re: IRQ_ONESHOT expectations vs mask/unmask Thomas Gleixner <tglx@linutronix.de> - 2017-07-31 09:10 +0200
  Re: IRQ_ONESHOT expectations vs mask/unmask Benjamin Herrenschmidt <benh@kernel.crashing.org> - 2017-07-31 10:40 +0200
    Re: IRQ_ONESHOT expectations vs mask/unmask Thomas Gleixner <tglx@linutronix.de> - 2017-07-31 10:50 +0200

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