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Groups > linux.kernel > #1701708
| From | Jernej Škrabec <jernej.skrabec@siol.net> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [linux-sunxi] [PATCH 07/13] ARM: sun8i: h3: add display engine pipeline barebone |
| Date | 2017-08-02 06:50 +0200 |
| Message-ID | <u9TLA-5cd-13@gated-at.bofh.it> (permalink) |
| References | <u9Ffz-4tk-3@gated-at.bofh.it> <u9FyX-4zN-35@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
Hi Icenowy,
Dne torek, 01. avgust 2017 ob 15:12:58 CEST je Icenowy Zheng napisal(a):
> As we have already the support for the DE2 on Allwinner H3, add the
> display engine pipeline device tree nodes to its DTSI file.
>
> The H5 pipeline has some differences and will be enabled later.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> arch/arm/boot/dts/sun8i-h3.dtsi | 170
> ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 170 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi
> b/arch/arm/boot/dts/sun8i-h3.dtsi index b36f9f423c39..75ad7b65a7fc 100644
> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
> @@ -41,6 +41,8 @@
> */
>
> #include "sunxi-h3-h5.dtsi"
> +#include <dt-bindings/clock/sun8i-de2.h>
> +#include <dt-bindings/reset/sun8i-de2.h>
>
> / {
> cpus {
> @@ -72,6 +74,174 @@
> };
> };
>
> + de: display-engine {
> + compatible = "allwinner,sun8i-h3-display-engine";
> + allwinner,pipelines = <&mixer0>,
> + <&mixer1>;
> + status = "disabled";
> + };
> +
> + soc {
> + display_clocks: clock@1000000 {
> + compatible = "allwinner,sun8i-a83t-de2-clk";
> + reg = <0x01000000 0x100000>;
> + clocks = <&ccu CLK_BUS_DE>,
> + <&ccu CLK_DE>;
> + clock-names = "bus",
> + "mod";
> + resets = <&ccu RST_BUS_DE>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + assigned-clocks = <&ccu CLK_DE>;
> + assigned-clock-parents = <&ccu CLK_PLL_DE>;
> + assigned-clock-rates = <432000000>;
> + };
I believe Maxime ask you to use clk_set_rate() in the past:
http://lists.infradead.org/pipermail/linux-arm-kernel/2017-June/512909.html
Regards,
Jernej
> +
> + mixer0: mixer@1100000 {
> + compatible = "allwinner,sun8i-h3-de2-mixer0";
> + reg = <0x01100000 0x100000>;
> + clocks = <&display_clocks CLK_BUS_MIXER0>,
> + <&display_clocks CLK_MIXER0>;
> + clock-names = "bus",
> + "mod";
> + resets = <&display_clocks RST_MIXER0>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + mixer0_out: port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> +
> + mixer0_out_tcon0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&tcon0_in_mixer0>;
> + };
> +
> + mixer0_out_tcon1: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&tcon1_in_mixer0>;
> + };
> + };
> + };
> + };
> +
> + mixer1: mixer@1200000 {
> + compatible = "allwinner,sun8i-h3-de2-mixer1";
> + reg = <0x01200000 0x100000>;
> + clocks = <&display_clocks CLK_BUS_MIXER1>,
> + <&display_clocks CLK_MIXER1>;
> + clock-names = "bus",
> + "mod";
> + resets = <&display_clocks RST_WB>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + mixer1_out: port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> +
> + mixer1_out_tcon0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&tcon0_in_mixer1>;
> + };
> +
> + mixer1_out_tcon1: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&tcon1_in_mixer1>;
> + };
> + };
> + };
> + };
> +
> + tcon0: lcd-controller@1c0c000 {
> + compatible = "allwinner,sun8i-h3-tcon";
> + reg = <0x01c0c000 0x1000>;
> + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_TCON0>,
> + <&ccu CLK_TCON0>;
> + clock-names = "ahb",
> + "tcon-ch1";
> + resets = <&ccu RST_BUS_TCON0>;
> + reset-names = "lcd";
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tcon0_in: port@0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> +
> + tcon0_in_mixer0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&mixer0_out_tcon0>;
> + };
> +
> + tcon0_in_mixer1: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&mixer1_out_tcon0>;
> + };
> + };
> +
> + tcon0_out: port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> + };
> + };
> + };
> +
> + tcon1: lcd-controller@1c0d000 {
> + compatible = "allwinner,sun8i-h3-tcon";
> + reg = <0x01c0d000 0x1000>;
> + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_TCON1>,
> + <&ccu CLK_TVE>;
> + clock-names = "ahb",
> + "tcon-ch1";
> + resets = <&ccu RST_BUS_TCON1>;
> + reset-names = "lcd";
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tcon1_in: port@0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> +
> + tcon1_in_mixer0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&mixer0_out_tcon1>;
> + };
> +
> + tcon1_in_mixer1: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&mixer1_out_tcon1>;
> + };
> + };
> +
> + tcon1_out: port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> + };
> + };
> + };
> + };
> +
> timer {
> compatible = "arm,armv7-timer";
> interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
> --
> 2.13.0
>
> --
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[PATCH 00/13] Allwinner H3 DE2 basical support Icenowy Zheng <icenowy@aosc.io> - 2017-08-01 15:20 +0200
[PATCH 03/13] drm: sun4i: add support for H3's TCON Icenowy Zheng <icenowy@aosc.io> - 2017-08-01 15:20 +0200
Re: [linux-sunxi] [PATCH 03/13] drm: sun4i: add support for H3's TCON Chen-Yu Tsai <wens@csie.org> - 2017-08-04 06:10 +0200
[PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support Icenowy Zheng <icenowy@aosc.io> - 2017-08-01 15:20 +0200
Re: [linux-sunxi] [PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support Jernej Škrabec <jernej.skrabec@siol.net> - 2017-08-02 07:00 +0200
Re: [linux-sunxi] [PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support icenowy@aosc.io - 2017-08-02 07:10 +0200
Re: [linux-sunxi] [PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support Jernej Škrabec <jernej.skrabec@siol.net> - 2017-08-02 21:10 +0200
Re: [linux-sunxi] [PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support Icenowy Zheng <icenowy@aosc.io> - 2017-08-03 01:00 +0200
Re: [linux-sunxi] [PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support Rob Herring <robh@kernel.org> - 2017-08-10 02:30 +0200
Re: [PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support Rob Herring <robh@kernel.org> - 2017-08-10 02:20 +0200
[PATCH 04/13] drm: sun4i: add compatible for H3 display engine Icenowy Zheng <icenowy@aosc.io> - 2017-08-01 15:40 +0200
[PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock Icenowy Zheng <icenowy@aosc.io> - 2017-08-01 15:40 +0200
Re: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock Chen-Yu Tsai <wens@csie.org> - 2017-08-04 06:20 +0200
Re: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock Icenowy Zheng <icenowy@aosc.io> - 2017-08-04 06:20 +0200
Re: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock Chen-Yu Tsai <wens@csie.org> - 2017-08-04 06:40 +0200
Re: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock Jernej Škrabec <jernej.skrabec@siol.net> - 2017-08-04 11:00 +0200
Re: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock Icenowy Zheng <icenowy@aosc.io> - 2017-08-04 11:10 +0200
Re: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock Chen-Yu Tsai <wens@csie.org> - 2017-08-04 11:40 +0200
Re: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock Chen-Yu Tsai <wens@csie.org> - 2017-08-04 11:30 +0200
Re: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock Jernej Škrabec <jernej.skrabec@siol.net> - 2017-08-04 15:50 +0200
Re: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock Chen-Yu Tsai <wens@csie.org> - 2017-08-04 16:20 +0200
[PATCH 09/13] [NOT FOR REVIEW NOW] drm: bridge: Add a pre_init function for the dw_hdmi driver Icenowy Zheng <icenowy@aosc.io> - 2017-08-01 15:40 +0200
[PATCH 08/13] [NOT FOR REVIEW NOW] drm: bridge: Enable polling hpd event in dw_hdmi Icenowy Zheng <icenowy@aosc.io> - 2017-08-01 15:40 +0200
[PATCH 07/13] ARM: sun8i: h3: add display engine pipeline barebone Icenowy Zheng <icenowy@aosc.io> - 2017-08-01 15:40 +0200
Re: [linux-sunxi] [PATCH 07/13] ARM: sun8i: h3: add display engine pipeline barebone Jernej Škrabec <jernej.skrabec@siol.net> - 2017-08-02 06:50 +0200
Re: [linux-sunxi] [PATCH 07/13] ARM: sun8i: h3: add display engine pipeline barebone icenowy@aosc.io - 2017-08-02 07:10 +0200
[PATCH 05/13] clk: sunxi-ng: allow CLK_DE to set CLK_PLL_DE for H3 Icenowy Zheng <icenowy@aosc.io> - 2017-08-01 15:40 +0200
[PATCH 06/13] clk: sunxi-ng: export CLK_PLL_DE for H3 Icenowy Zheng <icenowy@aosc.io> - 2017-08-01 15:40 +0200
[PATCH 12/13] [NOT FOR REVIEW NOW] ARM: sun8i: h3: enable DesignWare HDMI controller Icenowy Zheng <icenowy@aosc.io> - 2017-08-01 15:50 +0200
[PATCH 13/13] [NOT FOR REVIEW NOW] ARM: sun8i: h3: enable HDMI output on Orange Pi PC Icenowy Zheng <icenowy@aosc.io> - 2017-08-01 15:50 +0200
[PATCH 11/13] [NOT FOR REVIEW NOW] drm: sun4i: Add a glue for the DesignWare HDMI controller in H3 Icenowy Zheng <icenowy@aosc.io> - 2017-08-01 15:50 +0200
Re: [linux-sunxi] [PATCH 00/13] Allwinner H3 DE2 basical support Chen-Yu Tsai <wens@csie.org> - 2017-08-02 06:50 +0200
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