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Re: [PATCH v5 3/3] KVM: nVMX: Emulate EPTP switching for the L1 hypervisor

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2017-07-28 15:52-0400, Bandan Das:
> When L2 uses vmfunc, L0 utilizes the associated vmexit to
> emulate a switching of the ept pointer by reloading the
> guest MMU.
> 
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Bandan Das <bsd@redhat.com>
> ---
> diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
> @@ -7767,6 +7781,85 @@ static int handle_preemption_timer(struct kvm_vcpu *vcpu)
>  	return 1;
>  }
>  
> +static bool check_ept_address_valid(struct kvm_vcpu *vcpu, u64 address)
> +{
> +	struct vcpu_vmx *vmx = to_vmx(vcpu);
> +	u64 mask = VMX_EPT_RWX_MASK;
> +	int maxphyaddr = cpuid_maxphyaddr(vcpu);
> +	struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
> +
> +	/* Check for execute_only validity */
> +	if ((address & mask) == VMX_EPT_EXECUTABLE_MASK) {
> +		if (!(vmx->nested.nested_vmx_ept_caps &
> +		      VMX_EPT_EXECUTE_ONLY_BIT))
> +			return false;
> +	}

This checks looks wrong ... bits 0:2 define the memory type:

  0 = Uncacheable (UC)
  6 = Write-back (WB)

If those are supported MSR IA32_VMX_EPT_VPID_CAP, so I think it should
return false when

  (address & 0x7) == 0 && !(vmx->nested.nested_vmx_ept_caps & VMX_EPTP_UC_BIT))

the same for 6 and VMX_EPTP_WB_BIT and unconditionally for the remaining
types.

Btw. when is TLB flushed after EPTP switching?

> @@ -10354,10 +10456,20 @@ static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
>  				vmx->nested.nested_vmx_entry_ctls_high))
>  		return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
>  
> -	if (nested_cpu_has_vmfunc(vmcs12) &&
> -	    (vmcs12->vm_function_control &
> -	     ~vmx->nested.nested_vmx_vmfunc_controls))
> -		return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
> +	if (nested_cpu_has_vmfunc(vmcs12)) {
> +		if (vmcs12->vm_function_control &
> +		    ~vmx->nested.nested_vmx_vmfunc_controls)
> +			return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
> +
> +		if (nested_cpu_has_eptp_switching(vmcs12)) {
> +			if (!nested_cpu_has_ept(vmcs12) ||
> +			    (vmcs12->eptp_list_address >>
> +			     cpuid_maxphyaddr(vcpu)) ||
> +			    !IS_ALIGNED(vmcs12->eptp_list_address, 4096))

page_address_valid() would make this check a bit nicer,

thanks.

> +				return VMXERR_ENTRY_INVALID_CONTROL_FIELD;

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Re: [PATCH v5 3/3] KVM: nVMX: Emulate EPTP switching for the L1  hypervisor Radim Krčmář <rkrcmar@redhat.com> - 2017-08-01 17:20 +0200
  Re: [PATCH v5 3/3] KVM: nVMX: Emulate EPTP switching for the L1 hypervisor Bandan Das <bsd@redhat.com> - 2017-08-01 20:40 +0200

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