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Groups > linux.kernel > #1697901
| From | Abhishek Sahu <absahu@codeaurora.org> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [RFC 00/12] Misc patches for QCOM clocks |
| Date | 2017-07-27 13:20 +0200 |
| Message-ID | <u7OZH-5qs-3@gated-at.bofh.it> (permalink) |
| Organization | linux.* mail to news gateway |
This patch series does the miscellaneous changes in different types of Qualcomm clock nodes which are required for IPQ8074 SoC. Following are the major changes in IPQ8074 for which the existing code does not have support. 1. Some of the IPQ8074 RCG2 has CFG_RCGR at offset 8 from CMD_RCGR instead of offset 4. Following are the register offsets of UBI RCG2 in Qualcomm IPQ8074. GCC_NSS_UBI0_CMD_RCGR: 0x1868100 GCC_NSS_UBI0_CFG_RCGR: 0x1868108 2. It uses Brammo and Huayra PLL’s for which the support is not available in existing alpha PLL code. 3. Its APSS and UBI PLL offsets are different although both are Huayra PLLs. 4. Some of the its divider should not be changed during frequency change. These code changes are generic and it can be used by other Qualcomm SoCs. The major change is taking the register offsets from PLL and RCG2 clock node. Since this patch series is touching common code so this has been raised as RFC. Abhishek Sahu (12): clk: qcom: support for register offsets from rcg2 clock node clk: qcom: flag for 64 bit CONFIG_CTL clk: qcom: support for alpha mode configuration clk: qcom: use offset from alpha pll node clk: qcom: fix 16 bit alpha support calculation Clk: qcom: support for dynamic updating the PLL clk: qcom: add flag for VCO operation clk: qcom: support for Huayra PLL clk: qcom: support for Brammo PLL clk: qcom: add read-only divider operations clk: qcom: add read-only alpha pll post divider operations clk: qcom: add parent map for regmap mux drivers/clk/qcom/clk-alpha-pll.c | 464 +++++++++++++++++++++++++++------- drivers/clk/qcom/clk-alpha-pll.h | 49 +++- drivers/clk/qcom/clk-rcg.h | 21 +- drivers/clk/qcom/clk-rcg2.c | 78 +++--- drivers/clk/qcom/clk-regmap-divider.c | 29 +++ drivers/clk/qcom/clk-regmap-divider.h | 1 + drivers/clk/qcom/clk-regmap-mux.c | 6 + drivers/clk/qcom/clk-regmap-mux.h | 2 + drivers/clk/qcom/common.h | 11 +- drivers/clk/qcom/gcc-ipq8074.c | 6 +- drivers/clk/qcom/gcc-msm8994.c | 12 +- drivers/clk/qcom/gcc-msm8996.c | 12 +- drivers/clk/qcom/mmcc-msm8996.c | 48 ++-- 13 files changed, 574 insertions(+), 165 deletions(-) -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
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[RFC 00/12] Misc patches for QCOM clocks Abhishek Sahu <absahu@codeaurora.org> - 2017-07-27 13:20 +0200
[RFC 12/12] clk: qcom: add parent map for regmap mux Abhishek Sahu <absahu@codeaurora.org> - 2017-07-27 13:20 +0200
[RFC 06/12] Clk: qcom: support for dynamic updating the PLL Abhishek Sahu <absahu@codeaurora.org> - 2017-07-27 13:20 +0200
Re: [RFC 06/12] Clk: qcom: support for dynamic updating the PLL Stephen Boyd <sboyd@codeaurora.org> - 2017-07-28 20:40 +0200
Re: [RFC 06/12] Clk: qcom: support for dynamic updating the PLL Abhishek Sahu <absahu@codeaurora.org> - 2017-07-30 16:00 +0200
[RFC 11/12] clk: qcom: add read-only alpha pll post divider operations Abhishek Sahu <absahu@codeaurora.org> - 2017-07-27 13:20 +0200
[RFC 10/12] clk: qcom: add read-only divider operations Abhishek Sahu <absahu@codeaurora.org> - 2017-07-27 13:20 +0200
[RFC 07/12] clk: qcom: add flag for VCO operation Abhishek Sahu <absahu@codeaurora.org> - 2017-07-27 13:20 +0200
[RFC 08/12] clk: qcom: support for Huayra PLL Abhishek Sahu <absahu@codeaurora.org> - 2017-07-27 13:20 +0200
[RFC 05/12] clk: qcom: fix 16 bit alpha support calculation Abhishek Sahu <absahu@codeaurora.org> - 2017-07-27 13:20 +0200
[RFC 09/12] clk: qcom: support for Brammo PLL Abhishek Sahu <absahu@codeaurora.org> - 2017-07-27 13:20 +0200
Re: [RFC 00/12] Misc patches for QCOM clocks Stephen Boyd <sboyd@codeaurora.org> - 2017-07-27 20:40 +0200
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