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Groups > linux.kernel > #1629363
| From | Marc Zyngier <marc.zyngier@arm.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH v3 15/18] arm64: arch_timer: Enable CNTVCT_EL0 trap if workaround is enabled |
| Date | 2017-04-24 11:40 +0200 |
| Message-ID | <tzIDn-5fx-25@gated-at.bofh.it> (permalink) |
| References | (2 earlier) <tzHnX-4Av-9@gated-at.bofh.it> <tzHnX-4Av-7@gated-at.bofh.it> <tzHxE-4Ds-21@gated-at.bofh.it> <tzHR0-4JU-9@gated-at.bofh.it> <tzIk2-59r-19@gated-at.bofh.it> |
| Organization | ARM Ltd |
On 24/04/17 10:14, Hanjun Guo wrote:
> On 2017/4/24 16:40, Marc Zyngier wrote:
>> On 24/04/17 09:25, Lixiaoping (Timmy) wrote:
>>> Hi Marc,
>>>
>>> Sorry about previous email's confidential info. Please forget it.
>>>
>>> +#define ESR_ELx_SYS64_ISS_SYS_CNTFRQ (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 14, 0, 0) | \
>>> + ESR_ELx_SYS64_ISS_DIR_READ)
>>>
>>> I think (3, 3, 14, 0, 0) should be (3, 3, 0, 14, 0)?
>> Thanks for spotting this. I assumed that the sys_reg() and
>> SR_ELx_SYS64_ISS_SYS_VAL() macros took their arguments in the same
>> order. That would have been too easy... ;-)
>>
>> Amended patch below, please let me know if it works for you.
>>
>> Thanks,
>>
>> M.
>>
>> >From 4444c86a97c1a487e12c319fdc197c88631d72b5 Mon Sep 17 00:00:00 2001
>> From: Marc Zyngier <marc.zyngier@arm.com>
>> Date: Mon, 24 Apr 2017 09:04:03 +0100
>> Subject: [PATCH] arm64: Add CNTFRQ_EL0 trap handler
>>
>> We now trap accesses to CNTVCT_EL0 when the counter is broken
>> enough to require the kernel to mediate the access. But it
>> turns out that some existing userspace (such as OpenMPI) do
>> probe for the counter frequency, leading to an UNDEF exception
>> as CNTVCT_EL0 and CNTFRQ_EL0 share the same control bit.
>>
>> The fix is to handle the exception the same way we do for CNTVCT_EL0.
>>
>> Fixes: a86bd139f2ae ("arm64: arch_timer: Enable CNTVCT_EL0 trap if workaround is enabled")
>> Reported-by: Hanjun Guo <guohanjun@huawei.com>
>> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
>> ---
>
> I tested this patch and the undefined instruction error is gone, I can
> get the FREQ in the user space now, thank you very much for the quick
> response.
>
> Tested-by: Hanjun Guo <guohanjun@huawei.com>
> Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Thanks for giving it a go. Catalin, can you queue this via the arm64 tree?
Thanks,
M.
--
Jazz is not dead. It just smells funny...
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Re: [PATCH v3 15/18] arm64: arch_timer: Enable CNTVCT_EL0 trap if workaround is enabled Marc Zyngier <marc.zyngier@arm.com> - 2017-04-24 10:20 +0200
RE: [PATCH v3 15/18] arm64: arch_timer: Enable CNTVCT_EL0 trap if workaround is enabled "Lixiaoping (Timmy)" <lixiaoping3@huawei.com> - 2017-04-24 10:30 +0200
Re: [PATCH v3 15/18] arm64: arch_timer: Enable CNTVCT_EL0 trap if workaround is enabled Marc Zyngier <marc.zyngier@arm.com> - 2017-04-24 10:50 +0200
Re: [PATCH v3 15/18] arm64: arch_timer: Enable CNTVCT_EL0 trap if workaround is enabled Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-24 11:20 +0200
Re: [PATCH v3 15/18] arm64: arch_timer: Enable CNTVCT_EL0 trap if workaround is enabled Hanjun Guo <guohanjun@huawei.com> - 2017-04-24 11:20 +0200
Re: [PATCH v3 15/18] arm64: arch_timer: Enable CNTVCT_EL0 trap if workaround is enabled Marc Zyngier <marc.zyngier@arm.com> - 2017-04-24 11:40 +0200
Re: [PATCH v3 15/18] arm64: arch_timer: Enable CNTVCT_EL0 trap if workaround is enabled Catalin Marinas <catalin.marinas@arm.com> - 2017-04-24 13:30 +0200
RE: [PATCH v3 15/18] arm64: arch_timer: Enable CNTVCT_EL0 trap if workaround is enabled "Lixiaoping (Timmy)" <lixiaoping3@huawei.com> - 2017-04-24 10:30 +0200
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