[tip:ras/core] x86/mce: Enable PPIN for Knights Landing/Mill

From	tip-bot for Piotr Luc <tipbot@zytor.com>
Newsgroups	linux.kernel
Subject	[tip:ras/core] x86/mce: Enable PPIN for Knights Landing/Mill
Date	2017-04-14 11:00 +0200
Message-ID	<tw5fb-7mS-13@gated-at.bofh.it> (permalink)
References	<tu2ls-8cD-7@gated-at.bofh.it> <tvTnH-82S-7@gated-at.bofh.it>
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Commit-ID:  9ea74f7c70cd5e408f1cfbda0e6836929f820d49
Gitweb:     http://git.kernel.org/tip/9ea74f7c70cd5e408f1cfbda0e6836929f820d49
Author:     Piotr Luc <piotr.luc@intel.com>
AuthorDate: Thu, 13 Apr 2017 22:10:56 +0200
Committer:  Thomas Gleixner <tglx@linutronix.de>
CommitDate: Fri, 14 Apr 2017 10:46:12 +0200

x86/mce: Enable PPIN for Knights Landing/Mill

Intel Xeon Phi processors (KNL and KNM) support PPIN as well, so add their
CPUIDs to the whitelist of supported processors.

Signed-off-by: Piotr Luc <piotr.luc@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/20170408172004.8463-1-piotr.luc@intel.com
Link: http://lkml.kernel.org/r/20170413201056.10525-1-bp@alien8.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

---
 arch/x86/kernel/cpu/mcheck/mce_intel.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c
index 190b3e6..e84db79 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_intel.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c
@@ -481,6 +481,9 @@ static void intel_ppin_init(struct cpuinfo_x86 *c)
 	case INTEL_FAM6_BROADWELL_XEON_D:
 	case INTEL_FAM6_BROADWELL_X:
 	case INTEL_FAM6_SKYLAKE_X:
+	case INTEL_FAM6_XEON_PHI_KNL:
+	case INTEL_FAM6_XEON_PHI_KNM:
+
 		if (rdmsrl_safe(MSR_PPIN_CTL, &val))
 			return;

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[PATCH] x86/mce: Enable PPIN for Knights Landing/Mill Borislav Petkov <bp@alien8.de> - 2017-04-13 22:20 +0200
  [tip:ras/core] x86/mce: Enable PPIN for Knights Landing/Mill tip-bot for Piotr Luc <tipbot@zytor.com> - 2017-04-14 11:00 +0200

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