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Re: [PATCH v1 1/7] mfd: intel_soc_pmic_bxtwc: fix TMU interrupt index

From Lee Jones <lee.jones@linaro.org>
Newsgroups linux.kernel
Subject Re: [PATCH v1 1/7] mfd: intel_soc_pmic_bxtwc: fix TMU interrupt index
Date 2017-04-12 23:10 +0200
Message-ID <tvxGy-1ob-17@gated-at.bofh.it> (permalink)
References <tuMHE-4zk-5@gated-at.bofh.it> <tvo0x-3nU-15@gated-at.bofh.it> <tvuIG-7vr-19@gated-at.bofh.it>
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On Wed, 12 Apr 2017, Sathyanarayanan Kuppuswamy Natarajan wrote:

> Hi Lee,
> 
> Thanks. Will remove the code segment in next version.

Please always reply inline.  Top posting is frowned upon.

> On Wed, Apr 12, 2017 at 3:45 AM, Lee Jones <lee.jones@linaro.org> wrote:
> > On Mon, 10 Apr 2017, sathyanarayanan.kuppuswamy@linux.intel.com wrote:
> >
> >> From: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
> >>
> >> TMU interrupts are registered as a separate interrupt chip, and
> >> hence it should start its interrupt index(BXTWC_TMU_IRQ) number
> >> from 0. But currently, BXTWC_TMU_IRQ is defined as part of enum
> >> bxtwc_irqs_level2 and its index value is 11. Since this index
> >> value is used when calculating .num_irqs of regmap_irq_chip_tmu,
> >> it incorrectly reports number of irqs as 12 instead of actual
> >> value of 1.
> >>
> >> static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = {
> >>       REGMAP_IRQ_REG(BXTWC_TMU_IRQ, 0, 0x06),
> >> };
> >>
> >> static struct regmap_irq_chip bxtwc_regmap_irq_chip_tmu = {
> >>       .name = "bxtwc_irq_chip_tmu",
> >>       .status_base = BXTWC_TMUIRQ,
> >>       .mask_base = BXTWC_MTMUIRQ,
> >>       .irqs = bxtwc_regmap_irqs_tmu,
> >>       .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_tmu),
> >>       .num_regs = 1,
> >> };
> >>
> >> This patch fixes this issue by creating new enum of tmu irqs and
> >> resetting its starting index to 0.
> >>
> >> Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
> >> ---
> >>  drivers/mfd/intel_soc_pmic_bxtwc.c | 5 ++++-
> >>  1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > Patch looks fine, but please remove the code segment from the commit
> > log.
> >
> > For the code:
> >
> > For my own reference:
> >   Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
> >
> >> diff --git a/drivers/mfd/intel_soc_pmic_bxtwc.c b/drivers/mfd/intel_soc_pmic_bxtwc.c
> >> index 699c8c7..bb18e20 100644
> >> --- a/drivers/mfd/intel_soc_pmic_bxtwc.c
> >> +++ b/drivers/mfd/intel_soc_pmic_bxtwc.c
> >> @@ -94,7 +94,10 @@ enum bxtwc_irqs_level2 {
> >>       BXTWC_GPIO0_IRQ,
> >>       BXTWC_GPIO1_IRQ,
> >>       BXTWC_CRIT_IRQ,
> >> -     BXTWC_TMU_IRQ,
> >> +};
> >> +
> >> +enum bxtwc_irqs_tmu {
> >> +     BXTWC_TMU_IRQ = 0,
> >>  };
> >>
> >>  static const struct regmap_irq bxtwc_regmap_irqs[] = {
> >
> 
> 
> 

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
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Thread

[PATCH v1 1/7] mfd: intel_soc_pmic_bxtwc: fix TMU interrupt index sathyanarayanan.kuppuswamy@linux.intel.com - 2017-04-10 21:00 +0200
  [PATCH v1 2/7] mfd: intel_soc_pmic_bxtwc: remove thermal second level irqs sathyanarayanan.kuppuswamy@linux.intel.com - 2017-04-10 21:00 +0200
    Re: [PATCH v1 2/7] mfd: intel_soc_pmic_bxtwc: remove thermal second  level irqs Lee Jones <lee.jones@linaro.org> - 2017-04-12 13:50 +0200
  [PATCH v1 5/7] gpio: gpio-wcove: use first level PMIC GPIO irq sathyanarayanan.kuppuswamy@linux.intel.com - 2017-04-10 21:00 +0200
  [PATCH v1 4/7] mfd: intel_soc_pmic_bxtwc: remove second level irq for gpio device sathyanarayanan.kuppuswamy@linux.intel.com - 2017-04-10 21:00 +0200
    Re: [PATCH v1 4/7] mfd: intel_soc_pmic_bxtwc: remove second level  irq for gpio device Lee Jones <lee.jones@linaro.org> - 2017-04-12 13:50 +0200
  [PATCH v1 6/7] mfd: intel_soc_pmic_bxtwc: use chained irqs for second level irq chips sathyanarayanan.kuppuswamy@linux.intel.com - 2017-04-10 21:00 +0200
    Re: [PATCH v1 6/7] mfd: intel_soc_pmic_bxtwc: use chained irqs for  second level irq chips Lee Jones <lee.jones@linaro.org> - 2017-04-12 14:00 +0200
      Re: [PATCH v1 6/7] mfd: intel_soc_pmic_bxtwc: use chained irqs for  second level irq chips sathyanarayanan kuppuswamy          <sathyanarayanan.kuppuswamy@linux.intel.com> - 2017-04-13 23:50 +0200
  Re: [PATCH v1 1/7] mfd: intel_soc_pmic_bxtwc: fix TMU interrupt index Lee Jones <lee.jones@linaro.org> - 2017-04-12 12:50 +0200
    Re: [PATCH v1 1/7] mfd: intel_soc_pmic_bxtwc: fix TMU interrupt index Sathyanarayanan Kuppuswamy Natarajan <sathyaosid@gmail.com> - 2017-04-12 20:00 +0200
      Re: [PATCH v1 1/7] mfd: intel_soc_pmic_bxtwc: fix TMU interrupt index Lee Jones <lee.jones@linaro.org> - 2017-04-12 23:10 +0200

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