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Groups > linux.kernel > #1622747
| From | Michael Neuling <mikey@neuling.org> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH 1/3] powernv:idle: Use correct IDLE_THREAD_BITS in POWER8/9 |
| Date | 2017-04-13 08:40 +0200 |
| Message-ID | <tvGAa-7ok-11@gated-at.bofh.it> (permalink) |
| References | <tvoWB-3Wi-5@gated-at.bofh.it> <tvoWB-3Wi-3@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On Wed, 2017-04-12 at 17:16 +0530, Gautham R. Shenoy wrote: > From: "Gautham R. Shenoy" <ego@linux.vnet.ibm.com> > > This patch ensures that POWER8 and POWER9 processors use the correct > value of IDLE_THREAD_BITS as POWER8 has 8 threads per core and hence > the IDLE_THREAD_BITS should be 0xFF while POWER9 has only 4 threads > per core and hence the IDLE_THREAD_BITS should be 0xF. Why don't we derive this from the device tree rather than hard wiring it per cpu type? Mikey > > Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com> > --- > arch/powerpc/include/asm/cpuidle.h | 3 ++- > arch/powerpc/kernel/idle_book3s.S | 9 ++++++--- > arch/powerpc/platforms/powernv/idle.c | 5 ++++- > 3 files changed, 12 insertions(+), 5 deletions(-) > > diff --git a/arch/powerpc/include/asm/cpuidle.h > b/arch/powerpc/include/asm/cpuidle.h > index 52586f9..fece6ca 100644 > --- a/arch/powerpc/include/asm/cpuidle.h > +++ b/arch/powerpc/include/asm/cpuidle.h > @@ -34,7 +34,8 @@ > #define PNV_CORE_IDLE_THREAD_WINKLE_BITS_SHIFT 8 > #define PNV_CORE_IDLE_THREAD_WINKLE_BITS 0x0000FF00 > > -#define PNV_CORE_IDLE_THREAD_BITS 0x000000FF > +#define PNV_CORE_IDLE_4THREAD_BITS 0x0000000F > +#define PNV_CORE_IDLE_8THREAD_BITS 0x000000FF > > /* > * ============================ NOTE ================================= > diff --git a/arch/powerpc/kernel/idle_book3s.S > b/arch/powerpc/kernel/idle_book3s.S > index 2b13fe2..9b747e9 100644 > --- a/arch/powerpc/kernel/idle_book3s.S > +++ b/arch/powerpc/kernel/idle_book3s.S > @@ -223,7 +223,7 @@ lwarx_loop1: > add r15,r15,r5 /* Add if winkle */ > andc r15,r15,r7 /* Clear thread bit */ > > - andi. r9,r15,PNV_CORE_IDLE_THREAD_BITS > + andi. r9,r15,PNV_CORE_IDLE_8THREAD_BITS > > /* > * If cr0 = 0, then current thread is the last thread of the core entering > @@ -582,8 +582,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) > stwcx. r15,0,r14 > bne- 1b > isync > - > - andi. r9,r15,PNV_CORE_IDLE_THREAD_BITS > +BEGIN_FTR_SECTION > + andi. r9,r15,PNV_CORE_IDLE_4THREAD_BITS > +FTR_SECTION_ELSE > + andi. r9,r15,PNV_CORE_IDLE_8THREAD_BITS > +ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300) > cmpwi cr2,r9,0 > > /* > diff --git a/arch/powerpc/platforms/powernv/idle.c > b/arch/powerpc/platforms/powernv/idle.c > index 445f30a..d46920b 100644 > --- a/arch/powerpc/platforms/powernv/idle.c > +++ b/arch/powerpc/platforms/powernv/idle.c > @@ -112,7 +112,10 @@ static void pnv_alloc_idle_core_states(void) > size_t paca_ptr_array_size; > > core_idle_state = kmalloc_node(sizeof(u32), GFP_KERNEL, > node); > - *core_idle_state = PNV_CORE_IDLE_THREAD_BITS; > + if (cpu_has_feature(CPU_FTR_ARCH_300)) > + *core_idle_state = PNV_CORE_IDLE_4THREAD_BITS; > + else > + *core_idle_state = PNV_CORE_IDLE_8THREAD_BITS; > paca_ptr_array_size = (threads_per_core * > sizeof(struct paca_struct *)); >
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[PATCH 1/3] powernv:idle: Use correct IDLE_THREAD_BITS in POWER8/9 "Gautham R. Shenoy" <ego@linux.vnet.ibm.com> - 2017-04-12 13:50 +0200
Re: [PATCH 1/3] powernv:idle: Use correct IDLE_THREAD_BITS in POWER8/9 Michael Neuling <mikey@neuling.org> - 2017-04-13 08:40 +0200
Re: [PATCH 1/3] powernv:idle: Use correct IDLE_THREAD_BITS in POWER8/9 Michael Ellerman <mpe@ellerman.id.au> - 2017-04-13 12:10 +0200
Re: [PATCH 1/3] powernv:idle: Use correct IDLE_THREAD_BITS in POWER8/9 Gautham R Shenoy <ego@linux.vnet.ibm.com> - 2017-04-13 13:40 +0200
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