Groups > linux.kernel > #1619791

Re: [PATCH v1] x86/mce: enable PPIN for Knights Landing/Mill

From	Borislav Petkov <bp@alien8.de>
Newsgroups	linux.kernel
Subject	Re: [PATCH v1] x86/mce: enable PPIN for Knights Landing/Mill
Date	2017-04-10 12:40 +0200
Message-ID	<tuETL-7TH-1@gated-at.bofh.it> (permalink)
References	<tu2ls-8cD-7@gated-at.bofh.it>
Organization	linux.* mail to news gateway

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On Sat, Apr 08, 2017 at 07:20:04PM +0200, Piotr Luc wrote:
> Intel Xeon Phi processors (KNL and KNM) do support PPIN as well, so we
> add their CPUIDs to the whitelist of supported processors.
> PPIN is a unique number that allows to determine origin of the CPU,
> from now on will be logged when an mce error occur.
> 
> Signed-off-by: Piotr Luc <piotr.luc@intel.com>
> ---
>  arch/x86/kernel/cpu/mcheck/mce_intel.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c
> index 190b3e6..f1c44c3 100644
> --- a/arch/x86/kernel/cpu/mcheck/mce_intel.c
> +++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c
> @@ -481,6 +481,8 @@ static void intel_ppin_init(struct cpuinfo_x86 *c)
>  	case INTEL_FAM6_BROADWELL_XEON_D:
>  	case INTEL_FAM6_BROADWELL_X:
>  	case INTEL_FAM6_SKYLAKE_X:
> +	case INTEL_FAM6_XEON_PHI_KNL:
> +	case INTEL_FAM6_XEON_PHI_KNM:
>  		if (rdmsrl_safe(MSR_PPIN_CTL, &val))
>  			return;
>  
> -- 

Applied, thanks.

-- 
Regards/Gruss,
    Boris.

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[PATCH v1] x86/mce: enable PPIN for Knights Landing/Mill Piotr Luc <piotr.luc@intel.com> - 2017-04-08 19:30 +0200
  Re: [PATCH v1] x86/mce: enable PPIN for Knights Landing/Mill Borislav Petkov <bp@alien8.de> - 2017-04-10 12:40 +0200

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