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Re: dwc2_hc_chhltd_intr_dma - ChHltd set errors?

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On 4/6/2017 1:03 AM, John Stultz wrote:
>
>
> On Wed, Apr 5, 2017 at 5:58 AM, Minas Harutyunyan
> <Minas.Harutyunyan@synopsys.com <mailto:Minas.Harutyunyan@synopsys.com>>
> wrote:
>> On 4/4/2017 11:03 PM, John Stultz wrote:
>>>
>>> I did notice when cating the regdump file, I saw:
>>> dwc2 f72c0000.usb: Mode Mismatch Interrupt: currently in Host mode
>>> twice. (You'll see it 4 times in the dmesg around 1077 as I cat'ed
>>> regdump again to verify it wasn't just chance).
>>>
>>> Let me know if there is anything else you need!
>>>
>>
>> Could you please apply attached patch and try again.
>
> Thanks for sending this out!
>
> So it didn't build against mainline, but I tweaked it a bit:
> -       if ((hsotg->core_params->dma_enable > 0 &&
> -            hsotg->core_params->dma_desc_enable <= 0) ||
> +       if ((hsotg->params.host_dma > 0 &&
> +            hsotg->params.dma_desc_enable <= 0) ||
>
>
> But I'm still seeing similar behavior:
> [   91.517417] dwc2 f72c0000.usb: dwc2_hc_chhltd_intr_dma: Channel 5 -
> ChHltd set, but reason is unknown
> [   91.526693] dwc2 f72c0000.usb: hcint 0x00000002, intsts 0x04000029
> [   91.533613] asix 1-1.2:1.0 eth0: asix_rx_fixup() Bad Header Length
> 0x8003a0cc, offset 1302
> [   91.534102] asix 1-1.2:1.0 eth0: asix_rx_fixup() Bad Header Length
> 0x73ff5a7d, offset 4
> [  169.116866] dwc2 f72c0000.usb: dwc2_hc_chhltd_intr_dma: Channel 1 -
> ChHltd set, but reason is unknown
> [  169.126146] dwc2 f72c0000.usb: hcint 0x00000002, intsts 0x06200029
> [  170.699334] asix 1-1.2:1.0 eth0: asix_rx_fixup() Bad Header Length
> 0x36000807, offset 68
>
> And I'm not seeing the "Channel can't be halted" error from the new logic.
>
> Full dmesg and regdump attached.
>
> Let me know if there is something else I should try.
>
> thanks
> -john
Ok. To enable full dwc2 debug messages, please set USB_DWC2_DEBUG and 
USB_DWC2_VERBOSE in Kernel configuration file.
Also provide the topology of connected devices(class, speed) to dwc2
root hub.
Thanks,
Minas

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Re: dwc2_hc_chhltd_intr_dma - ChHltd set errors? John Stultz <john.stultz@linaro.org> - 2017-04-01 01:10 +0200
  Re: dwc2_hc_chhltd_intr_dma - ChHltd set errors? John Youn <John.Youn@synopsys.com> - 2017-04-03 07:30 +0200
    Re: dwc2_hc_chhltd_intr_dma - ChHltd set errors? Minas Harutyunyan <Minas.Harutyunyan@synopsys.com> - 2017-04-03 15:00 +0200
      Re: dwc2_hc_chhltd_intr_dma - ChHltd set errors? John Stultz <john.stultz@linaro.org> - 2017-04-04 05:10 +0200
        Re: dwc2_hc_chhltd_intr_dma - ChHltd set errors? Minas Harutyunyan <Minas.Harutyunyan@synopsys.com> - 2017-04-04 09:20 +0200
          Re: dwc2_hc_chhltd_intr_dma - ChHltd set errors? Felipe Balbi <felipe.balbi@linux.intel.com> - 2017-04-04 09:40 +0200
            Re: dwc2_hc_chhltd_intr_dma - ChHltd set errors? Minas Harutyunyan <Minas.Harutyunyan@synopsys.com> - 2017-04-05 15:20 +0200
              Re: dwc2_hc_chhltd_intr_dma - ChHltd set errors? Minas Harutyunyan <Minas.Harutyunyan@synopsys.com> - 2017-04-06 09:50 +0200
                Re: dwc2_hc_chhltd_intr_dma - ChHltd set errors? Felipe Balbi <felipe.balbi@linux.intel.com> - 2017-04-07 10:20 +0200
                Re: dwc2_hc_chhltd_intr_dma - ChHltd set errors? Minas Harutyunyan <Minas.Harutyunyan@synopsys.com> - 2017-04-07 15:00 +0200

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