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Re: [PATCH v5 2/2] iio: Aspeed ADC

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On 04/01, Jonathan Cameron wrote:
> On 28/03/17 22:52, Rick Altherr wrote:
> > Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold
> > interrupts are supported by the hardware but are not currently implemented.
> > 
> > Signed-off-by: Rick Altherr <raltherr@google.com>
> Two really trivial things inline. I'll fix them whilst applying rather than
> having you do a v6 - please do sanity check I haven't messed it up though!
> 
> Applied to the togreg branch of iio.git and pushed out as testing for
> the autobuilders to play with it.
> 

Oh I was too late. Blame work. Anyway, I made some comments on
v4. If they're fixed in a later patch or discussed on list that's
fine. No worries on my end.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

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Thread

[PATCH v5 2/2] iio: Aspeed ADC Rick Altherr <raltherr@google.com> - 2017-03-29 00:00 +0200
  Re: [PATCH v5 2/2] iio: Aspeed ADC Joel Stanley <joel@jms.id.au> - 2017-03-29 04:40 +0200
    Re: [PATCH v5 2/2] iio: Aspeed ADC Xo Wang <xow@google.com> - 2017-03-31 23:00 +0200
      Re: [PATCH v5 2/2] iio: Aspeed ADC Jonathan Cameron <jic23@kernel.org> - 2017-04-01 13:00 +0200
  Re: [PATCH v5 2/2] iio: Aspeed ADC Jonathan Cameron <jic23@kernel.org> - 2017-04-01 13:00 +0200
    Re: [PATCH v5 2/2] iio: Aspeed ADC Stephen Boyd <sboyd@codeaurora.org> - 2017-04-06 00:00 +0200
      Re: [PATCH v5 2/2] iio: Aspeed ADC Jonathan Cameron <jic23@kernel.org> - 2017-04-08 18:20 +0200

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