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Groups > linux.kernel > #1616052
| From | Andy Shevchenko <andy.shevchenko@gmail.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH v5 6/6] platform/x86: intel_pmc_ipc: use gcr mem base for S0ix counter read |
| Date | 2017-04-04 16:00 +0200 |
| Message-ID | <tsxa3-5BM-27@gated-at.bofh.it> (permalink) |
| References | <tskwa-5IU-17@gated-at.bofh.it> <trZrI-es-9@gated-at.bofh.it> <tskw9-5IU-11@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On Tue, Apr 4, 2017 at 3:24 AM, Kuppuswamy Sathyanarayanan
<sathyanarayanan.kuppuswamy@linux.intel.com> wrote:
> To maintain the uniformity in accessing GCR registers, this patch
> modifies the S0ix counter read function to use GCR address base
> instead of ipc address base.
>
This one looks good.
--- 8< --- 8< ---
Overall, I do not like this spreading interface where we have more and
more functions which use some global variable without clear
understanding of device / initialization dependencies.
Better approach would be something using opaque pointers and API which
takes it as an input.
I didn't investigate yet about something similar to UCLASS_SYSCON
(this is nice model of dependency used in U-Boot) in Linux kernel, it
would be cool to use it.
So, the priority number #2 (number #1 is to fix interrupt handling for
Whiskey Cove) is to refactor this all mess.
Like we agreed it would be last series I'm going to apply without
refactoring done.
--- 8< --- 8< ---
> Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
> Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
> Tested-by: Shanth Murthy <shanth.murthy@intel.com>
> ---
> arch/x86/include/asm/intel_pmc_ipc.h | 2 ++
> drivers/platform/x86/intel_pmc_ipc.c | 10 +++-------
> 2 files changed, 5 insertions(+), 7 deletions(-)
>
> Changes since v4:
> * Rebased on top of latest changes.
>
> Changes since v3:
> * Rebased on top of latest changes.
>
> diff --git a/arch/x86/include/asm/intel_pmc_ipc.h b/arch/x86/include/asm/intel_pmc_ipc.h
> index 8402efe..fac89eb 100644
> --- a/arch/x86/include/asm/intel_pmc_ipc.h
> +++ b/arch/x86/include/asm/intel_pmc_ipc.h
> @@ -25,6 +25,8 @@
>
> /* GCR reg offsets from gcr base*/
> #define PMC_GCR_PMC_CFG_REG 0x08
> +#define PMC_GCR_TELEM_DEEP_S0IX_REG 0x78
> +#define PMC_GCR_TELEM_SHLW_S0IX_REG 0x80
>
> #if IS_ENABLED(CONFIG_INTEL_PMC_IPC)
>
> diff --git a/drivers/platform/x86/intel_pmc_ipc.c b/drivers/platform/x86/intel_pmc_ipc.c
> index 3d0d6f17..b61f569 100644
> --- a/drivers/platform/x86/intel_pmc_ipc.c
> +++ b/drivers/platform/x86/intel_pmc_ipc.c
> @@ -57,10 +57,6 @@
> #define IPC_WRITE_BUFFER 0x80
> #define IPC_READ_BUFFER 0x90
>
> -/* PMC Global Control Registers */
> -#define GCR_TELEM_DEEP_S0IX_OFFSET 0x1078
> -#define GCR_TELEM_SHLW_S0IX_OFFSET 0x1080
> -
> /* Residency with clock rate at 19.2MHz to usecs */
> #define S0IX_RESIDENCY_IN_USECS(d, s) \
> ({ \
> @@ -203,7 +199,7 @@ static inline u32 ipc_data_readl(u32 offset)
>
> static inline u64 gcr_data_readq(u32 offset)
> {
> - return readq(ipcdev.ipc_base + offset);
> + return readq(ipcdev.gcr_mem_base + offset);
> }
>
> static inline int is_gcr_valid(u32 offset)
> @@ -906,8 +902,8 @@ int intel_pmc_s0ix_counter_read(u64 *data)
> if (!ipcdev.has_gcr_regs)
> return -EACCES;
>
> - deep = gcr_data_readq(GCR_TELEM_DEEP_S0IX_OFFSET);
> - shlw = gcr_data_readq(GCR_TELEM_SHLW_S0IX_OFFSET);
> + deep = gcr_data_readq(PMC_GCR_TELEM_DEEP_S0IX_REG);
> + shlw = gcr_data_readq(PMC_GCR_TELEM_SHLW_S0IX_REG);
>
> *data = S0IX_RESIDENCY_IN_USECS(deep, shlw);
>
> --
> 2.7.4
>
--
With Best Regards,
Andy Shevchenko
Back to linux.kernel | Previous | Next — Previous in thread | Next in thread | Find similar | Unroll thread
Re: [PATCH v3 1/5] platform/x86: intel_pmc_ipc: fix gcr offset Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> - 2017-03-31 15:40 +0200
[PATCH v4 3/5] watchdog: iTCO_wdt: Add PMC specific noreboot update api Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> - 2017-04-01 01:40 +0200
Re: [PATCH v4 3/5] watchdog: iTCO_wdt: Add PMC specific noreboot update api Andy Shevchenko <andy.shevchenko@gmail.com> - 2017-04-02 16:10 +0200
Re: [PATCH v4 3/5] watchdog: iTCO_wdt: Add PMC specific noreboot update api Sathyanarayanan Kuppuswamy Natarajan <sathyaosid@gmail.com> - 2017-04-03 04:00 +0200
[PATCH v4 2/5] platform/x86: intel_pmc_ipc: Add pmc gcr read/write/update api's Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> - 2017-04-01 01:40 +0200
Re: [PATCH v4 2/5] platform/x86: intel_pmc_ipc: Add pmc gcr read/write/update api's Andy Shevchenko <andy.shevchenko@gmail.com> - 2017-04-02 16:00 +0200
Re: [PATCH v4 2/5] platform/x86: intel_pmc_ipc: Add pmc gcr read/write/update api's Sathyanarayanan Kuppuswamy Natarajan <sathyaosid@gmail.com> - 2017-04-03 04:00 +0200
Re: [PATCH v4 2/5] platform/x86: intel_pmc_ipc: Add pmc gcr read/write/update api's Andy Shevchenko <andy.shevchenko@gmail.com> - 2017-04-04 15:30 +0200
Re: [PATCH v4 2/5] platform/x86: intel_pmc_ipc: Add pmc gcr read/write/update api's sathyanarayanan kuppuswamy <sathyanarayanan.kuppuswamy@linux.intel.com> - 2017-04-04 22:30 +0200
[PATCH v4 5/5] platform/x86: intel_pmc_ipc: use gcr mem base for S0ix counter read Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> - 2017-04-01 01:40 +0200
[PATCH v4 4/5] platform/x86: intel_pmc_ipc: Fix iTCO GCS memory mapping failure Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> - 2017-04-01 01:40 +0200
Re: [PATCH v4 4/5] platform/x86: intel_pmc_ipc: Fix iTCO GCS memory mapping failure Andy Shevchenko <andy.shevchenko@gmail.com> - 2017-04-02 16:20 +0200
Re: [PATCH v4 4/5] platform/x86: intel_pmc_ipc: Fix iTCO GCS memory mapping failure Sathyanarayanan Kuppuswamy Natarajan <sathyaosid@gmail.com> - 2017-04-03 04:00 +0200
[PATCH v4 1/5] platform/x86: intel_pmc_ipc: fix gcr offset Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> - 2017-04-01 01:40 +0200
Re: [PATCH v4 1/5] platform/x86: intel_pmc_ipc: fix gcr offset Andy Shevchenko <andy.shevchenko@gmail.com> - 2017-04-02 16:20 +0200
Re: [PATCH v4 1/5] platform/x86: intel_pmc_ipc: fix gcr offset Sathyanarayanan Kuppuswamy Natarajan <sathyaosid@gmail.com> - 2017-04-03 04:00 +0200
[PATCH v5 4/6] watchdog: iTCO_wdt: cleanup set/unset no_reboot calls Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> - 2017-04-04 02:30 +0200
Re: [PATCH v5 4/6] watchdog: iTCO_wdt: cleanup set/unset no_reboot calls Guenter Roeck <linux@roeck-us.net> - 2017-04-04 05:30 +0200
Re: [PATCH v5 4/6] watchdog: iTCO_wdt: cleanup set/unset no_reboot calls Andy Shevchenko <andy.shevchenko@gmail.com> - 2017-04-04 16:00 +0200
[PATCH v5 2/6] platform/x86: intel_pmc_ipc: Add pmc gcr read/write/update api's Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> - 2017-04-04 02:30 +0200
Re: [PATCH v5 2/6] platform/x86: intel_pmc_ipc: Add pmc gcr read/write/update api's Andy Shevchenko <andy.shevchenko@gmail.com> - 2017-04-04 16:00 +0200
Re: [PATCH v5 2/6] platform/x86: intel_pmc_ipc: Add pmc gcr read/write/update api's sathyanarayanan kuppuswamy <sathyanarayanan.kuppuswamy@linux.intel.com> - 2017-04-05 00:20 +0200
[PATCH v5 6/6] platform/x86: intel_pmc_ipc: use gcr mem base for S0ix counter read Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> - 2017-04-04 02:30 +0200
Re: [PATCH v5 6/6] platform/x86: intel_pmc_ipc: use gcr mem base for S0ix counter read Andy Shevchenko <andy.shevchenko@gmail.com> - 2017-04-04 16:00 +0200
Re: [PATCH v5 6/6] platform/x86: intel_pmc_ipc: use gcr mem base for S0ix counter read sathyanarayanan kuppuswamy <sathyanarayanan.kuppuswamy@linux.intel.com> - 2017-04-05 00:20 +0200
[PATCH v5 1/6] platform/x86: intel_pmc_ipc: fix gcr offset Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> - 2017-04-04 02:30 +0200
[PATCH v5 3/6] watchdog: iTCO_wdt: Add PMC specific noreboot update api Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> - 2017-04-04 02:30 +0200
Re: [PATCH v5 3/6] watchdog: iTCO_wdt: Add PMC specific noreboot update api Andy Shevchenko <andy.shevchenko@gmail.com> - 2017-04-04 15:50 +0200
[PATCH v5 5/6] platform/x86: intel_pmc_ipc: Fix iTCO_wdt GCS memory mapping failure Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> - 2017-04-04 02:30 +0200
Re: [PATCH v5 5/6] platform/x86: intel_pmc_ipc: Fix iTCO_wdt GCS memory mapping failure Andy Shevchenko <andy.shevchenko@gmail.com> - 2017-04-04 16:00 +0200
Re: [PATCH v4 1/5] platform/x86: intel_pmc_ipc: fix gcr offset Andy Shevchenko <andy.shevchenko@gmail.com> - 2017-04-04 15:30 +0200
Re: [PATCH v4 1/5] platform/x86: intel_pmc_ipc: fix gcr offset sathyanarayanan kuppuswamy <sathyanarayanan.kuppuswamy@linux.intel.com> - 2017-04-04 23:40 +0200
[PATCH v6 6/6] platform/x86: intel_pmc_ipc: use gcr mem base for S0ix counter read Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> - 2017-04-06 01:00 +0200
[PATCH v6 5/6] platform/x86: intel_pmc_ipc: Fix iTCO_wdt GCS memory mapping failure Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> - 2017-04-06 01:00 +0200
Re: [PATCH v6 5/6] platform/x86: intel_pmc_ipc: Fix iTCO_wdt GCS memory mapping failure Andy Shevchenko <andy.shevchenko@gmail.com> - 2017-04-06 23:40 +0200
[PATCH v6 3/6] watchdog: iTCO_wdt: cleanup set/unset no_reboot_bit functions Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> - 2017-04-06 01:00 +0200
[PATCH v6 2/6] platform/x86: intel_pmc_ipc: Add pmc gcr read/write/update api's Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> - 2017-04-06 01:00 +0200
[PATCH v6 4/6] watchdog: iTCO_wdt: Add PMC specific noreboot update api Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> - 2017-04-06 01:00 +0200
Re: [PATCH v6 4/6] watchdog: iTCO_wdt: Add PMC specific noreboot update api Guenter Roeck <linux@roeck-us.net> - 2017-04-06 13:50 +0200
[PATCH v6 1/6] platform/x86: intel_pmc_ipc: fix gcr offset Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> - 2017-04-06 01:00 +0200
Re: [PATCH v6 1/6] platform/x86: intel_pmc_ipc: fix gcr offset Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> - 2017-04-06 17:20 +0200
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