Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]
Groups > linux.kernel > #1615898
| Path | csiph.com!feeder.erje.net!2.eu.feeder.erje.net!news.unit0.net!news.panservice.it!bofh.it!news.nic.it!robomod |
|---|---|
| From | Anurup M <anurupvasu@gmail.com> |
| Newsgroups | linux.kernel |
| Subject | [PATCH v7 9/9] dts: arm64: hip07: Add Hisilicon SoC PMU support |
| Date | Tue, 04 Apr 2017 13:00:01 +0200 |
| Message-ID | <tsulP-3L5-13@gated-at.bofh.it> (permalink) |
| Dkim-Signature | v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=sPqlXXC5KVSBAcQGtLDvysnSrNgs3cxuXLPqv4q/rno=; b=gnzqmbV6sl7nFq7QlhnyCa7F71X/x8AQ+13rYN6Wpw9XrNfh3G4SL9BIGuHfumOvIf RB2i0Cd53rJYA05VcA923GpzYFPYQC7lzRnoZfLDxomcSyKUvSS+r7GQ05VKEs/QXI2l msVJ8DXRX8vSJZIgswz63jRn5jOHsNMuqbHHHoTK3tpjKD4Ox6PqUpJyWZDM6SynML/u Q4ZwdQTvq58yTlCFpUnNbOb0+p6uU/l+Z/30P+vgc8cpMfQ2khiZh7aZvab0vt2+QtZg lTXFuZWXnpGh7Erq2l1m5FWGXV8MiVlu2s9LRUlLHmi3boxLIbXVgsJuJcZxuBspFEx7 KVYQ== |
| X-Google-Dkim-Signature | v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=sPqlXXC5KVSBAcQGtLDvysnSrNgs3cxuXLPqv4q/rno=; b=NJDzmFgB4gsrDSX2/eJ20KZleBIAyjwekpprQY7Y21AJ1A0qHwQ/dbAl5wUQcOyWlb rBqH1QQ4u2xAvNCSy4cueeCRJgYMO4pjNOAg70hEkFy399+9Rz3U3btZuY73MrTd6bhi GgWdES09bVWGMrvVrwcpC39bggc+teJQKSc/MQauZzIo3fz0NUDpA5I7jjcCAQtaJF+y GUprGFBsmaH1vrbJsAfw6yu3jqfM2j7zSLSbnVaQ4RrAMRcxF8Ri/smaFdBw6Ti7hPHW 9Grxn08U4kz+aCBjEJTYu2oLNg3Rlj0pgd2867NzkvQFgzZSGoUzbVto5OSxYhwY7ElU SRfg== |
| X-Gm-Message-State | AFeK/H2+VjM9yWGkbb9OSLkReU+jn+ievJrPF8Wm9anInC1DPbOpz58dLZfJAzRWlBJ+qw== |
| X-Received | by 10.99.127.23 with SMTP id a23mr22925228pgd.155.1491303413075; Tue, 04 Apr 2017 03:56:53 -0700 (PDT) |
| X-Google-Original-From | Anurup M <anurup.m@huawei.com> |
| X-Mailer | git-send-email 2.1.4 |
| Sender | robomod@news.nic.it |
| List-ID | <linux-kernel.vger.kernel.org> |
| X-Mailing-List | linux-kernel@vger.kernel.org |
| Approved | robomod@news.nic.it |
| Lines | 105 |
| Organization | linux.* mail to news gateway |
| X-Original-Cc | devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, anurup.m@huawei.com, zhangshaokun@hisilicon.com, tanxiaojun@huawei.com, sanil.kumar@hisilicon.com, john.garry@huawei.com, gabriele.paoloni@huawei.com, shiju.jose@huawei.com, huangdaode@hisilicon.com, linuxarm@huawei.com, dikshit.n@huawei.com, shyju.pv@huawei.com, anurupvasu@gmail.com |
| X-Original-Date | Tue, 4 Apr 2017 06:56:42 -0400 |
| X-Original-Message-ID | <1491303402-140597-1-git-send-email-anurup.m@huawei.com> |
| X-Original-Sender | linux-kernel-owner@vger.kernel.org |
| Xref | csiph.com linux.kernel:1615898 |
Show key headers only | View raw
Add nodes for djtag, L3 cache and MN to support uncore events.
Signed-off-by: Anurup M <anurup.m@huawei.com>
---
arch/arm64/boot/dts/hisilicon/hip07.dtsi | 87 ++++++++++++++++++++++++++++++++
1 file changed, 87 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
index 5144eb1..1099f6e 100644
--- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
@@ -1056,4 +1056,91 @@
status = "disabled";
};
};
+
+ djtag0: djtag@60010000 {
+ compatible = "hisilicon,hip07-cpu-djtag-v2";
+ reg = <0x0 0x60010000 0x0 0x10000>;
+ hisilicon,scl-id = <0x03>;
+
+ /* L3 cache bank 0 for socket0 CPU die scl#3 */
+ pmul3c0 {
+ compatible = "hisilicon,hip07-pmu-l3c-v2";
+ hisilicon,module-id = <0x01>;
+ hisilicon,instance-id = <0x01>;
+ };
+
+ /* L3 cache bank 1 for socket0 CPU die scl#3 */
+ pmul3c1 {
+ compatible = "hisilicon,hip07-pmu-l3c-v2";
+ hisilicon,module-id = <0x02>;
+ hisilicon,instance-id = <0x01>;
+ };
+
+ /* L3 cache bank 2 for socket0 CPU die scl#3 */
+ pmul3c2 {
+ compatible = "hisilicon,hip07-pmu-l3c-v2";
+ hisilicon,module-id = <0x03>;
+ hisilicon,instance-id = <0x01>;
+ };
+
+ /* L3 cache bank 3 for socket0 CPU die scl#3 */
+ pmul3c3 {
+ compatible = "hisilicon,hip07-pmu-l3c-v2";
+ hisilicon,module-id = <0x04>;
+ hisilicon,instance-id = <0x01>;
+ };
+
+ /*
+ * Miscellaneous node for socket0
+ * CPU die scl#3
+ */
+ pmumn0 {
+ compatible = "hisilicon,hip07-pmu-mn-v2";
+ hisilicon,module-id = <0x21>;
+ };
+ };
+
+ djtag1: djtag@40010000 {
+ compatible = "hisilicon,hip07-cpu-djtag-v2";
+ reg = <0x0 0x40010000 0x0 0x10000>;
+ hisilicon,scl-id = <0x01>;
+
+ /* L3 cache bank 0 for socket0 CPU die scl#1 */
+ pmul3c0 {
+ compatible = "hisilicon,hip07-pmu-l3c-v2";
+ hisilicon,module-id = <0x01>;
+ hisilicon,instance-id = <0x01>;
+ };
+
+ /* L3 cache bank 1 for socket0 CPU die scl#1 */
+ pmul3c1 {
+ compatible = "hisilicon,hip07-pmu-l3c-v2";
+ hisilicon,module-id = <0x02>;
+ hisilicon,instance-id = <0x01>;
+ };
+
+ /* L3 cache bank 2 for socket0 CPU die scl#1 */
+ pmul3c2 {
+ compatible = "hisilicon,hip07-pmu-l3c-v2";
+ hisilicon,module-id = <0x03>;
+ hisilicon,instance-id = <0x01>;
+ };
+
+ /* L3 cache bank 3 for socket0 CPU die scl#1 */
+ pmul3c3 {
+ compatible = "hisilicon,hip07-pmu-l3c-v2";
+ hisilicon,module-id = <0x04>;
+ hisilicon,instance-id = <0x01>;
+ };
+
+ /*
+ * Miscellaneous node for socket0
+ * CPU die scl#1
+ */
+ pmumn1 {
+ compatible = "hisilicon,hip07-pmu-mn-v2";
+ hisilicon,module-id = <0x21>;
+ };
+ };
+
};
--
2.1.4
Back to linux.kernel | Previous | Next | Find similar | Unroll thread
[PATCH v7 9/9] dts: arm64: hip07: Add Hisilicon SoC PMU support Anurup M <anurupvasu@gmail.com> - 2017-04-04 13:00 +0200
csiph-web