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Groups > linux.kernel > #1615223
| From | Thierry Reding <thierry.reding@gmail.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH 2/3] dt-bindings: Add bindings for nvidia,tegra186-ccplex-cluster |
| Date | 2017-04-03 16:10 +0200 |
| Message-ID | <tsaQ9-7U5-1@gated-at.bofh.it> (permalink) |
| References | <ts9AK-6V6-9@gated-at.bofh.it> <ts9AK-6V6-13@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
[Multipart message — attachments visible in raw view] - view raw
On Mon, Apr 03, 2017 at 03:42:24PM +0300, Mikko Perttunen wrote:
> The Tegra186 CCPLEX_CLUSTER area contains memory-mapped
> registers that initiate CPU frequency/voltage transitions.
>
> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
> ---
> .../arm/tegra/nvidia,tegra186-ccplex-cluster.txt | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt
> new file mode 100644
> index 000000000000..50cd615219e9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt
> @@ -0,0 +1,22 @@
> +NVIDIA Tegra CCPLEX_CLUSTER area
> +
> +Required properties:
> +- compatible: Should contain one of the following:
> + - "nvidia,tegra186-ccplex-cluster": for Tegra186
> +- reg: Must contain an (offset, length) pair of the register set for each
> + entry in reg-names.
> +- reg-names: Must include the following entries:
> + - "a57": Public aperture for A57 CPU cluster
> + - "denver": Public aperture for Denver CPU cluster
> +- nvidia,bpmp: Phandle to BPMP device that can be queried for OPP tables
"phandle"
> +Example:
> +
> + ccplex@e000000 {
> + compatible = "nvidia,tegra186-ccplex-cluster";
> + reg = <0x0 0x0e060000 0x0 0x1000>,
> + <0x0 0x0e070000 0x0 0x1000>;
> + reg-names = "a57", "denver";
> +
> + nvidia,bpmp = <&bpmp>;
> + };
Where's the information about the register offsets coming from? The TRM
says that CCPLEX_CLUSTER has a single aperture from 0x0e000000 to
0x0e3fffff.
Thierry
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[PATCH 1/3] cpufreq: Add Tegra186 cpufreq driver Mikko Perttunen <mperttunen@nvidia.com> - 2017-04-03 14:50 +0200
[PATCH 2/3] dt-bindings: Add bindings for nvidia,tegra186-ccplex-cluster Mikko Perttunen <mperttunen@nvidia.com> - 2017-04-03 14:50 +0200
Re: [PATCH 2/3] dt-bindings: Add bindings for nvidia,tegra186-ccplex-cluster Thierry Reding <thierry.reding@gmail.com> - 2017-04-03 16:10 +0200
Re: [PATCH 2/3] dt-bindings: Add bindings for nvidia,tegra186-ccplex-cluster Mikko Perttunen <cyndis@kapsi.fi> - 2017-04-03 17:20 +0200
Re: [PATCH 2/3] dt-bindings: Add bindings for nvidia,tegra186-ccplex-cluster Jon Hunter <jonathanh@nvidia.com> - 2017-04-03 16:30 +0200
Re: [PATCH 2/3] dt-bindings: Add bindings for nvidia,tegra186-ccplex-cluster Mikko Perttunen <cyndis@kapsi.fi> - 2017-04-03 17:20 +0200
[PATCH 3/3] arm64: tegra: Add CCPLEX_CLUSTER area in Tegra186 Mikko Perttunen <mperttunen@nvidia.com> - 2017-04-03 14:50 +0200
Re: [PATCH 1/3] cpufreq: Add Tegra186 cpufreq driver Thierry Reding <thierry.reding@gmail.com> - 2017-04-03 16:50 +0200
Re: [PATCH 1/3] cpufreq: Add Tegra186 cpufreq driver Mikko Perttunen <cyndis@kapsi.fi> - 2017-04-03 17:50 +0200
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