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Groups > linux.kernel > #1616232
| From | Marc Zyngier <marc.zyngier@arm.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH v3 03/18] arm64: Define Cortex-A73 MIDR |
| Date | 2017-04-04 19:30 +0200 |
| Message-ID | <tsArf-7Vm-1@gated-at.bofh.it> (permalink) |
| References | <tsAhz-7QC-7@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
As we're about to introduce a new workaround that is specific to Cortex-A73, let's define the coresponding MIDR. Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index fc502713ab37..0984d1b3a8f2 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -80,6 +80,7 @@ #define ARM_CPU_PART_FOUNDATION 0xD00 #define ARM_CPU_PART_CORTEX_A57 0xD07 #define ARM_CPU_PART_CORTEX_A53 0xD03 +#define ARM_CPU_PART_CORTEX_A73 0xD09 #define APM_CPU_PART_POTENZA 0x000 @@ -92,6 +93,7 @@ #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) +#define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1) -- 2.11.0
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[PATCH v3 00/18] clocksource/arch_timer: Errata workaround infrastructure rework Marc Zyngier <marc.zyngier@arm.com> - 2017-04-04 19:20 +0200
[PATCH v3 06/18] arm64: arch_timer: Add infrastructure for multiple erratum detection methods Marc Zyngier <marc.zyngier@arm.com> - 2017-04-04 19:20 +0200
[PATCH v3 02/18] arm64: Add CNTVCT_EL0 trap handler Marc Zyngier <marc.zyngier@arm.com> - 2017-04-04 19:20 +0200
[PATCH v3 18/18] arm64: arch_timer: Add HISILICON_ERRATUM_161010101 ACPI matching data Marc Zyngier <marc.zyngier@arm.com> - 2017-04-04 19:20 +0200
[PATCH v3 17/18] arm64: arch_timer: Allow erratum matching with ACPI OEM information Marc Zyngier <marc.zyngier@arm.com> - 2017-04-04 19:20 +0200
[PATCH v3 15/18] arm64: arch_timer: Enable CNTVCT_EL0 trap if workaround is enabled Marc Zyngier <marc.zyngier@arm.com> - 2017-04-04 19:20 +0200
[PATCH v3 12/18] arm64: arch_timer: Allows a CPU-specific erratum to only affect a subset of CPUs Marc Zyngier <marc.zyngier@arm.com> - 2017-04-04 19:20 +0200
[PATCH v3 03/18] arm64: Define Cortex-A73 MIDR Marc Zyngier <marc.zyngier@arm.com> - 2017-04-04 19:30 +0200
[PATCH v3 09/18] arm64: arch_timer: Get rid of erratum_workaround_set_sne Marc Zyngier <marc.zyngier@arm.com> - 2017-04-04 19:30 +0200
[PATCH v3 13/18] arm64: arch_timer: Move clocksource_counter and co around Marc Zyngier <marc.zyngier@arm.com> - 2017-04-04 19:30 +0200
[PATCH v3 14/18] arm64: arch_timer: Save cntkctl_el1 as a per-cpu variable Marc Zyngier <marc.zyngier@arm.com> - 2017-04-04 19:30 +0200
[PATCH v3 07/18] arm64: arch_timer: Add erratum handler for CPU-specific capability Marc Zyngier <marc.zyngier@arm.com> - 2017-04-04 19:30 +0200
[PATCH v3 11/18] arm64: arch_timer: Make workaround methods optional Marc Zyngier <marc.zyngier@arm.com> - 2017-04-04 19:30 +0200
[PATCH v3 01/18] arm64: Allow checking of a CPU-local erratum Marc Zyngier <marc.zyngier@arm.com> - 2017-04-04 19:30 +0200
[PATCH v3 16/18] arm64: arch_timer: Workaround for Cortex-A73 erratum 858921 Marc Zyngier <marc.zyngier@arm.com> - 2017-04-04 19:30 +0200
[PATCH v3 10/18] arm64: arch_timer: Rework the set_next_event workarounds Marc Zyngier <marc.zyngier@arm.com> - 2017-04-04 19:30 +0200
[PATCH v3 08/18] arm64: arch_timer: Move arch_timer_reg_read/write around Marc Zyngier <marc.zyngier@arm.com> - 2017-04-04 19:30 +0200
Re: [PATCH v3 00/18] clocksource/arch_timer: Errata workaround infrastructure rework Catalin Marinas <catalin.marinas@arm.com> - 2017-04-06 18:30 +0200
Re: [PATCH v3 00/18] clocksource/arch_timer: Errata workaround infrastructure rework Thomas Gleixner <tglx@linutronix.de> - 2017-04-07 10:20 +0200
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