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Groups > linux.kernel > #1609441
| From | Andy Tang <andy.tang@nxp.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk |
| Date | 2017-03-27 05:50 +0200 |
| Message-ID | <tptPk-1FP-3@gated-at.bofh.it> (permalink) |
| References | <tptPk-1FP-5@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
PING! Regards, Yuantian > -----Original Message----- > From: Yuantian Tang [mailto:andy.tang@nxp.com] > Sent: Monday, March 20, 2017 10:37 AM > To: mturquette@baylibre.com > Cc: sboyd@codeaurora.org; robh+dt@kernel.org; mark.rutland@arm.com; > linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux- > kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Scott Wood; > Andy Tang > Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk > > From: Scott Wood <oss@buserror.net> > > ls1012a has separate input root clocks for core PLLs versus the platform PLL, > with the latter described as sysclk in the hw docs. > Update the qoriq-clock binding to allow a second input clock, named > "coreclk". If present, this clock will be used for the core PLLs. > > Signed-off-by: Scott Wood <oss@buserror.net> > Signed-off-by: Tang Yuantian <andy.tang@nxp.com> > Acked-by: Rob Herring <robh@kernel.org> > --- > v2: > -- change the author to Scott > Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt > b/Documentation/devicetree/bindings/clock/qoriq-clock.txt > index aa3526f..119cafd 100644 > --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt > +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt > @@ -56,6 +56,11 @@ Optional properties: > - clocks: If clock-frequency is not specified, sysclk may be provided > as an input clock. Either clock-frequency or clocks must be > provided. > + A second input clock, called "coreclk", may be provided if > + core PLLs are based on a different input clock from the > + platform PLL. > +- clock-names: Required if a coreclk is present. Valid names are > + "sysclk" and "coreclk". > > 2. Clock Provider > > @@ -72,6 +77,7 @@ second cell is the clock index for the specified type. > 2 hwaccel index (n in CLKCGnHWACSR) > 3 fman 0 for fm1, 1 for fm2 > 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4 > + 5 coreclk must be 0 > > 3. Example > > -- > 2.1.0.27.g96db324
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RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk Andy Tang <andy.tang@nxp.com> - 2017-03-27 05:50 +0200
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