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Re: [PATCH v5 2/4] fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.

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Hi Matthew,

On Wed, 22 Mar 2017 09:08:18 -0700 (PDT)
matthew.gerlach@linux.intel.com matthew.gerlach@linux.intel.com wrote:
...
>> Can we also add a function for registering a PCIe device with
>> PR IP here? Something like:  
>
>If we have an alt_pr_pcie_register function, we will need the 
>corresponding alt_pr_pcie_unregister function.  Both of these functions 
>should go into their own file like alt_pr_platform_probe() and 
>alt_pr_platform_remove().

Okay, thanks.

>> /**
>> * alt_pr_pcie_register - register PCIe device with PR-IP core
>> * @pci_dev:    PCI device with PR-IP
>> * @bar:        PR-IP BAR number
>> * @pr_offset:  offset of the PR-IP core registers
>> *
>> * Return: 0 on success, negative error code otherwise.
>> *
>> * To unregister the PCIe device, use alt_pr_unregister(&pdev->dev).
>> */
>> int alt_pr_pcie_register(struct pci_dev *pdev, int bar, int pr_offset)
>> {
>>        void __iomem *base;
>>        int ret;
>>
>>        if (!pci_is_enabled(pdev)) {
>>                ret = pci_enable_device(pdev);
>>                if (ret < 0) {
>>                        dev_err(&pdev->dev, "can't enable device: %d\n", ret);
>>                        return ret;
>>                }
>>        }
>>
>>        base = devm_ioremap_resource(&pdev->dev, &pdev->resource[bar]);  
>
>Does this remap the whole bar?  If it does, what happens if other 
>components are also connected to the bar?  How do those corresponding 
>drivers get access to the mapped memory?

yes, it remaps the whole bar. I do not know the details of the PR IP,
my assumption was that PR IP it is only one component in the bar.
Then I could use devm_ioremap() instead. Thanks for the hint!

Anatolij

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Re: [PATCH v5 2/4] fpga pr ip: Core driver support for Altera  Partial Reconfiguration IP. Anatolij Gustschin <agust@denx.de> - 2017-03-21 22:20 +0100
  Re: [PATCH v5 2/4] fpga pr ip: Core driver support for Altera Partial  Reconfiguration IP. matthew.gerlach@linux.intel.com - 2017-03-22 17:10 +0100
    Re: [PATCH v5 2/4] fpga pr ip: Core driver support for Altera  Partial Reconfiguration IP. Anatolij Gustschin <agust@denx.de> - 2017-03-22 17:50 +0100

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