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Groups > linux.kernel > #1604853
| From | Marc Zyngier <marc.zyngier@arm.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH v2 11/18] arm64: arch_timer: Rework the set_next_event workarounds |
| Date | 2017-03-20 19:00 +0100 |
| Message-ID | <tn9L3-89w-5@gated-at.bofh.it> (permalink) |
| References | <tn9Bn-85C-1@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
The way we work around errata affecting set_next_event is not very
nice, at it imposes this workaround on errata that do not need it.
Add new workaround hooks and let the existing workarounds use them.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
arch/arm64/include/asm/arch_timer.h | 4 ++++
drivers/clocksource/arm_arch_timer.c | 30 ++++++++++++++++++++++++++----
2 files changed, 30 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h
index e5325299aa6d..58572d38e9db 100644
--- a/arch/arm64/include/asm/arch_timer.h
+++ b/arch/arm64/include/asm/arch_timer.h
@@ -43,6 +43,8 @@ enum arch_timer_erratum_match_type {
ate_match_local_cap_id,
};
+struct clock_event_device;
+
struct arch_timer_erratum_workaround {
enum arch_timer_erratum_match_type match_type;
const void *id;
@@ -50,6 +52,8 @@ struct arch_timer_erratum_workaround {
u32 (*read_cntp_tval_el0)(void);
u32 (*read_cntv_tval_el0)(void);
u64 (*read_cntvct_el0)(void);
+ int (*set_next_event_phys)(unsigned long, struct clock_event_device *);
+ int (*set_next_event_virt)(unsigned long, struct clock_event_device *);
};
extern const struct arch_timer_erratum_workaround *timer_unstable_counter_workaround;
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 4caafbdefb9d..b9f01daafdfa 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -282,6 +282,8 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = {
.read_cntp_tval_el0 = fsl_a008585_read_cntp_tval_el0,
.read_cntv_tval_el0 = fsl_a008585_read_cntv_tval_el0,
.read_cntvct_el0 = fsl_a008585_read_cntvct_el0,
+ .set_next_event_phys = erratum_set_next_event_tval_phys,
+ .set_next_event_virt = erratum_set_next_event_tval_virt,
},
#endif
#ifdef CONFIG_HISILICON_ERRATUM_161010101
@@ -292,6 +294,8 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = {
.read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0,
.read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0,
.read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
+ .set_next_event_phys = erratum_set_next_event_tval_phys,
+ .set_next_event_virt = erratum_set_next_event_tval_virt,
},
#endif
};
@@ -384,10 +388,24 @@ static void arch_timer_check_ool_workaround(enum arch_timer_erratum_match_type t
local ? "local" : "global", wa->desc);
}
+#define erratum_handler(fn, r, ...) \
+({ \
+ bool __val; \
+ if (needs_unstable_timer_counter_workaround() && \
+ timer_unstable_counter_workaround->fn) { \
+ r = timer_unstable_counter_workaround->fn(__VA_ARGS__); \
+ __val = true; \
+ } else { \
+ __val = false; \
+ } \
+ __val; \
+})
+
#else
#define arch_timer_check_ool_workaround(t,a) do { } while(0)
#define erratum_set_next_event_tval_virt(...) ({BUG(); 0;})
#define erratum_set_next_event_tval_phys(...) ({BUG(); 0;})
+#define erratum_handler(fn, r, ...) ({false;})
#endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */
static __always_inline irqreturn_t timer_handler(const int access,
@@ -480,8 +498,10 @@ static __always_inline void set_next_event(const int access, unsigned long evt,
static int arch_timer_set_next_event_virt(unsigned long evt,
struct clock_event_device *clk)
{
- if (needs_unstable_timer_counter_workaround())
- return erratum_set_next_event_tval_virt(evt, clk);
+ int ret;
+
+ if (erratum_handler(set_next_event_virt, ret, evt, clk))
+ return ret;
set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
return 0;
@@ -490,8 +510,10 @@ static int arch_timer_set_next_event_virt(unsigned long evt,
static int arch_timer_set_next_event_phys(unsigned long evt,
struct clock_event_device *clk)
{
- if (needs_unstable_timer_counter_workaround())
- return erratum_set_next_event_tval_phys(evt, clk);
+ int ret;
+
+ if (erratum_handler(set_next_event_phys, ret, evt, clk))
+ return ret;
set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
return 0;
--
2.11.0
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[PATCH v2 00/18] clocksource/arch_timer: Errata workaround infrastructure rework Marc Zyngier <marc.zyngier@arm.com> - 2017-03-20 18:50 +0100
[PATCH v2 01/18] arm64: Allow checking of a CPU-local erratum Marc Zyngier <marc.zyngier@arm.com> - 2017-03-20 18:50 +0100
Re: [PATCH v2 01/18] arm64: Allow checking of a CPU-local erratum Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-03-22 10:30 +0100
[PATCH v2 11/18] arm64: arch_timer: Rework the set_next_event workarounds Marc Zyngier <marc.zyngier@arm.com> - 2017-03-20 19:00 +0100
[PATCH v2 08/18] arm64: arch_timer: Add erratum handler for CPU-specific capability Marc Zyngier <marc.zyngier@arm.com> - 2017-03-20 19:00 +0100
[PATCH v2 05/18] arm64: cpu_errata: Add capability to advertise Cortex-A73 erratum 858921 Marc Zyngier <marc.zyngier@arm.com> - 2017-03-20 19:00 +0100
Re: [PATCH v2 05/18] arm64: cpu_errata: Add capability to advertise Cortex-A73 erratum 858921 Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-03-22 16:10 +0100
[PATCH v2 09/18] arm64: arch_timer: Move arch_timer_reg_read/write around Marc Zyngier <marc.zyngier@arm.com> - 2017-03-20 19:00 +0100
Re: [PATCH v2 09/18] arm64: arch_timer: Move arch_timer_reg_read/write around Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-03-22 17:00 +0100
[PATCH v2 07/18] arm64: arch_timer: Add erratum handler for globally defined capability Marc Zyngier <marc.zyngier@arm.com> - 2017-03-20 19:00 +0100
[PATCH v2 06/18] arm64: arch_timer: Add infrastructure for multiple erratum detection methods Marc Zyngier <marc.zyngier@arm.com> - 2017-03-20 19:40 +0100
Re: [PATCH v2 06/18] arm64: arch_timer: Add infrastructure for multiple erratum detection methods Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-03-22 16:50 +0100
Re: [PATCH v2 06/18] arm64: arch_timer: Add infrastructure for multiple erratum detection methods Marc Zyngier <marc.zyngier@arm.com> - 2017-03-22 17:00 +0100
Re: [PATCH v2 06/18] arm64: arch_timer: Add infrastructure for multiple erratum detection methods Marc Zyngier <marc.zyngier@arm.com> - 2017-03-22 17:00 +0100
Re: [PATCH v2 06/18] arm64: arch_timer: Add infrastructure for multiple erratum detection methods Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-03-22 18:10 +0100
Re: [PATCH v2 06/18] arm64: arch_timer: Add infrastructure for multiple erratum detection methods Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-03-23 18:40 +0100
Re: [PATCH v2 06/18] arm64: arch_timer: Add infrastructure for multiple erratum detection methods Marc Zyngier <marc.zyngier@arm.com> - 2017-03-24 15:00 +0100
Re: [PATCH v2 06/18] arm64: arch_timer: Add infrastructure for multiple erratum detection methods Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-03-27 10:00 +0200
Re: [PATCH v2 06/18] arm64: arch_timer: Add infrastructure for multiple erratum detection methods dann frazier <dann.frazier@canonical.com> - 2017-03-24 18:50 +0100
Re: [PATCH v2 06/18] arm64: arch_timer: Add infrastructure for multiple erratum detection methods Marc Zyngier <marc.zyngier@arm.com> - 2017-03-24 19:20 +0100
[PATCH v2 15/18] arm64: arch_timer: Enable CNTVCT_EL0 trap if workaround is enabled Marc Zyngier <marc.zyngier@arm.com> - 2017-03-20 19:40 +0100
[PATCH v2 16/18] arm64: arch_timer: Workaround for Cortex-A73 erratum 858921 Marc Zyngier <marc.zyngier@arm.com> - 2017-03-20 19:40 +0100
[PATCH v2 13/18] arm64: arch_timer: Allows a CPU-specific erratum to only affect a subset of CPUs Marc Zyngier <marc.zyngier@arm.com> - 2017-03-20 19:40 +0100
[PATCH v2 04/18] arm64: cpu_errata: Allow an erratum to be match for all revisions of a core Marc Zyngier <marc.zyngier@arm.com> - 2017-03-20 19:40 +0100
Re: [PATCH v2 04/18] arm64: cpu_errata: Allow an erratum to be match for all revisions of a core Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-03-22 16:10 +0100
[PATCH v2 18/18] arm64: arch_timer: Add HISILICON_ERRATUM_161010101 ACPI matching data Marc Zyngier <marc.zyngier@arm.com> - 2017-03-20 19:40 +0100
[PATCH v2 02/18] arm64: Add CNTVCT_EL0 trap handler Marc Zyngier <marc.zyngier@arm.com> - 2017-03-20 19:40 +0100
[PATCH v2 03/18] arm64: Define Cortex-A73 MIDR Marc Zyngier <marc.zyngier@arm.com> - 2017-03-20 19:40 +0100
[PATCH v2 17/18] arm64: arch_timer: Allow erratum matching with ACPI OEM information Marc Zyngier <marc.zyngier@arm.com> - 2017-03-20 19:40 +0100
[PATCH v2 10/18] arm64: arch_timer: Get rid of erratum_workaround_set_sne Marc Zyngier <marc.zyngier@arm.com> - 2017-03-20 19:50 +0100
[PATCH v2 12/18] arm64: arch_timer: Make workaround methods optional Marc Zyngier <marc.zyngier@arm.com> - 2017-03-20 19:50 +0100
[PATCH v2 14/18] arm64: arch_timer: Move clocksource_counter and co around Marc Zyngier <marc.zyngier@arm.com> - 2017-03-20 19:50 +0100
Re: [PATCH v2 00/18] clocksource/arch_timer: Errata workaround infrastructure rework Ding Tianhong <dingtianhong@huawei.com> - 2017-03-22 15:00 +0100
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