Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]
Groups > linux.kernel > #1603027
| Path | csiph.com!aioe.org!news.servidellagleba.it!bofh.it!news.nic.it!robomod |
|---|---|
| From | Chris Zhong <zyw@rock-chips.com> |
| Newsgroups | linux.kernel |
| Subject | [PATCH v3 4/4] drm/rockchip/dsi: correct the grf_switch_reg name |
| Date | Fri, 17 Mar 2017 05:10:02 +0100 |
| Message-ID | <tlRnc-l0-9@gated-at.bofh.it> (permalink) |
| References | <tlRnb-l0-5@gated-at.bofh.it> |
| X-Google-Dkim-Signature | v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zgXmYBmngMx1Ladt0rLl/5g+/99XCPIRfjDGWY/JsS8=; b=aRfOOCnVdBQUWpo0FRQ7VlP0bTuCZhV8HQFMw0p6zzgbXB7r/IkNytZU//k6ZL3jCt ZMEUvM+XxP1Vrh+WGmCLqwZWo4Yn+Zkc7OcJqEllp2UuZFElYJgO9V7R1pu5AsHYS38Y TvVqkpOTjwU/yF70hpBDXVxFLJbDZhGTa8C4skguhh/tvTE+/H0kZncqdO0vW28dZd2c YyXeMcHuuFQltDfSMts38nxABN6HNaBOmZE66uwQzrKiCsEj95FQveRd3i62a4Sp5yRQ M5O84kWKdSx9CZq5Wa+uH2UyTfhtqm+xV223GH6nvV8/f6k7/RVcVOPgl/6/lWpF8V7j Q29w== |
| X-Gm-Message-State | AFeK/H38xuaaU4xqLWVq3xNqOzuJfXYTJKFKUTgZWRayhHhj14pkg14weqNxaglAFF4CRQ== |
| X-Received | by 10.98.11.8 with SMTP id t8mr14266908pfi.195.1489722884837; Thu, 16 Mar 2017 20:54:44 -0700 (PDT) |
| X-Mailer | git-send-email 2.6.3 |
| Sender | robomod@news.nic.it |
| List-ID | <linux-kernel.vger.kernel.org> |
| X-Mailing-List | linux-kernel@vger.kernel.org |
| Approved | robomod@news.nic.it |
| Lines | 36 |
| Organization | linux.* mail to news gateway |
| X-Original-Cc | Chris Zhong <zyw@rock-chips.com>, Mark Yao <mark.yao@rock-chips.com>, David Airlie <airlied@linux.ie>, Heiko Stuebner <heiko@sntech.de>, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org |
| X-Original-Date | Fri, 17 Mar 2017 11:54:24 +0800 |
| X-Original-Message-ID | <1489722865-22122-5-git-send-email-zyw@rock-chips.com> |
| X-Original-References | <1489722865-22122-1-git-send-email-zyw@rock-chips.com> |
| X-Original-Sender | linux-kernel-owner@vger.kernel.org |
| Xref | csiph.com linux.kernel:1603027 |
Show key headers only | View raw
For the RK3399, the grf_switch_reg name should be RK3399_GRF_SOC_CON20,
not RK3399_GRF_SOC_CON19.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
---
Changes in v3: None
Changes in v2: None
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index 5a18281..19b9208 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -34,7 +34,7 @@
#define RK3288_DSI0_SEL_VOP_LIT BIT(6)
#define RK3288_DSI1_SEL_VOP_LIT BIT(9)
-#define RK3399_GRF_SOC_CON19 0x6250
+#define RK3399_GRF_SOC_CON20 0x6250
#define RK3399_DSI0_SEL_VOP_LIT BIT(0)
#define RK3399_DSI1_SEL_VOP_LIT BIT(4)
@@ -1151,7 +1151,7 @@ static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = {
static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
.dsi0_en_bit = RK3399_DSI0_SEL_VOP_LIT,
.dsi1_en_bit = RK3399_DSI1_SEL_VOP_LIT,
- .grf_switch_reg = RK3399_GRF_SOC_CON19,
+ .grf_switch_reg = RK3399_GRF_SOC_CON20,
.grf_dsi0_mode = RK3399_GRF_DSI_MODE,
.grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22,
.flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
--
2.6.3
Back to linux.kernel | Previous | Next — Previous in thread | Next in thread | Find similar | Unroll thread
[PATCH v3 0/4] RK3399 dw-mipi-dsi patches Chris Zhong <zyw@rock-chips.com> - 2017-03-17 05:10 +0100
[PATCH v3 4/4] drm/rockchip/dsi: correct the grf_switch_reg name Chris Zhong <zyw@rock-chips.com> - 2017-03-17 05:10 +0100
Re: [PATCH v3 4/4] drm/rockchip/dsi: correct the grf_switch_reg name Brian Norris <briannorris@chromium.org> - 2017-03-21 21:10 +0100
Re: [PATCH v3 4/4] drm/rockchip/dsi: correct the grf_switch_reg name Sean Paul <seanpaul@chromium.org> - 2017-03-21 21:20 +0100
[PATCH v3 3/4] drm/rockchip/dsi: enable the grf clk before writing grf registers Chris Zhong <zyw@rock-chips.com> - 2017-03-17 05:10 +0100
Re: [PATCH v3 3/4] drm/rockchip/dsi: enable the grf clk before writing grf registers Sean Paul <seanpaul@chromium.org> - 2017-03-21 21:40 +0100
[PATCH v3 1/4] drm/rockchip/dsi: check phy_cfg_clk only for RK3399 Chris Zhong <zyw@rock-chips.com> - 2017-03-17 05:10 +0100
Re: [PATCH v3 1/4] drm/rockchip/dsi: check phy_cfg_clk only for RK3399 Sean Paul <seanpaul@chromium.org> - 2017-03-21 21:20 +0100
Re: [PATCH v3 1/4] drm/rockchip/dsi: check phy_cfg_clk only for RK3399 Sean Paul <seanpaul@chromium.org> - 2017-03-21 21:40 +0100
[PATCH v3 2/4] dt-bindings: add the grf clock for dw-mipi-dsi Chris Zhong <zyw@rock-chips.com> - 2017-03-17 05:10 +0100
Re: [PATCH v3 2/4] dt-bindings: add the grf clock for dw-mipi-dsi Sean Paul <seanpaul@chromium.org> - 2017-03-21 21:20 +0100
Re: [PATCH v3 2/4] dt-bindings: add the grf clock for dw-mipi-dsi Sean Paul <seanpaul@chromium.org> - 2017-03-21 21:30 +0100
Re: [PATCH v3 0/4] RK3399 dw-mipi-dsi patches Brian Norris <briannorris@chromium.org> - 2017-03-21 21:10 +0100
csiph-web