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Re: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on

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On 13/03/17 10:45, Peter De Schrijver wrote:
> On Wed, Mar 08, 2017 at 11:48:21AM +0000, Jon Hunter wrote:
>>
>> On 08/03/17 11:38, Geert Uytterhoeven wrote:
>>> Hi Jon,
>>>
>>> On Wed, Mar 8, 2017 at 11:13 AM, Jon Hunter <jonathanh@nvidia.com> wrote:
>>>>> I had a similar issue with SH-Mobile AG5, where the power domain containing
>>>>> the JTAG interface is powered down.
>>>>
>>>> This reminds me, does your patch assume that the DFD power domain is
>>>> enabled? I am guessing that it needs to be for JTAG to work.
>>>
>>> Yes. The pm-rmobile driver looks for "arm,coresight-etm3x" devices, and
>>> marks the corresponding PM Domain as always-on, as long as the
>>> Coresight code doesn't handle runtime PM.
>>
>> Sorry Geert, but I was asking Peter specifically about the power-domain
>> on Tegra as I have a feeling we may have the same scenario ;-)
> 
> We don't have a specific power domain for DFD on Tegra210. It's part of the
> non-powergateable core domain.

Either we are getting our wires crossed or the TRM is wrong :-(

 static const char * const tegra210_powergates[] = {
         [TEGRA_POWERGATE_CPU] = "crail",
         [TEGRA_POWERGATE_3D] = "3d",
         [TEGRA_POWERGATE_VENC] = "venc",
         [TEGRA_POWERGATE_PCIE] = "pcie",
         [TEGRA_POWERGATE_MPE] = "mpe",
         [TEGRA_POWERGATE_SATA] = "sata",
         [TEGRA_POWERGATE_CPU1] = "cpu1",
         [TEGRA_POWERGATE_CPU2] = "cpu2",
         [TEGRA_POWERGATE_CPU3] = "cpu3",
         [TEGRA_POWERGATE_CPU0] = "cpu0",
         [TEGRA_POWERGATE_C0NC] = "c0nc",
         [TEGRA_POWERGATE_SOR] = "sor",
         [TEGRA_POWERGATE_DIS] = "dis",
         [TEGRA_POWERGATE_DISB] = "disb",
         [TEGRA_POWERGATE_XUSBA] = "xusba",
         [TEGRA_POWERGATE_XUSBB] = "xusbb",
         [TEGRA_POWERGATE_XUSBC] = "xusbc",
         [TEGRA_POWERGATE_VIC] = "vic",
         [TEGRA_POWERGATE_IRAM] = "iram",
         [TEGRA_POWERGATE_NVDEC] = "nvdec",
         [TEGRA_POWERGATE_NVJPG] = "nvjpg",
         [TEGRA_POWERGATE_AUD] = "aud",
         [TEGRA_POWERGATE_DFD] = "dfd",
         [TEGRA_POWERGATE_VE2] = "ve2",
 };


Jon

-- 
nvpublic

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Re: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on Jon Hunter <jonathanh@nvidia.com> - 2017-03-02 22:30 +0100
  Re: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-03-06 09:40 +0100
    Re: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on Jon Hunter <jonathanh@nvidia.com> - 2017-03-06 11:10 +0100
      Re: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-03-06 15:40 +0100
        Re: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on Jon Hunter <jonathanh@nvidia.com> - 2017-03-06 17:00 +0100
        Re: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on Geert Uytterhoeven <geert@linux-m68k.org> - 2017-03-06 18:00 +0100
          Re: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on Jon Hunter <jonathanh@nvidia.com> - 2017-03-07 21:30 +0100
            Re: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on Geert Uytterhoeven <geert@linux-m68k.org> - 2017-03-08 11:20 +0100
          Re: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on Jon Hunter <jonathanh@nvidia.com> - 2017-03-08 12:30 +0100
            Re: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on Geert Uytterhoeven <geert@linux-m68k.org> - 2017-03-08 12:50 +0100
              Re: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on Jon Hunter <jonathanh@nvidia.com> - 2017-03-08 13:20 +0100
                Re: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-03-13 11:50 +0100
                Re: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on Jon Hunter <jonathanh@nvidia.com> - 2017-03-13 12:10 +0100
                Re: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-03-13 15:20 +0100
          Re: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-03-13 11:50 +0100

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