Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support

From	Joao Pinto <Joao.Pinto@synopsys.com>
Newsgroups	linux.kernel
Subject	Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support
Date	2017-03-08 16:40 +0100
Message-ID	<tiLQZ-8we-1@gated-at.bofh.it> (permalink)
References	(4 earlier) <timpA-7rg-25@gated-at.bofh.it> <tiI6K-5Wo-5@gated-at.bofh.it> <tiIgq-5ZP-9@gated-at.bofh.it> <tiIgq-5ZP-19@gated-at.bofh.it> <tiLQZ-8we-3@gated-at.bofh.it>
Organization	linux.* mail to news gateway

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Às 1:31 PM de 3/8/2017, Kishon Vijay Abraham I escreveu:
> Hi,
> 
> On Wednesday 08 March 2017 05:07 PM, Joao Pinto wrote:
>> Às 11:35 AM de 3/8/2017, Kishon Vijay Abraham I escreveu:
>>> Hi,
>>>
>>> On Wednesday 08 March 2017 05:02 PM, Joao Pinto wrote:
>>>>
>>>> Hi Kishon,
>>>>
>>>>>> Can you provide PCIE_GET_ATU_INB_UNR_REG_OFFSET (similar to
>>>>>> PCIE_GET_ATU_OUTB_UNR_REG_OFFSET)?
>>>>>
>>>>> Yes of course, I will send you the definition soon.
>>>>
>>>> As promissed here is the definition for Inbound:
>>>>
>>>> +/* register address builder */
>>>> +#define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register)		\
>>>> +					((0x3 << 20) | (region << 9) |	\
>>>> +					(0x1 << 8) | (register << 2))
>>>
>>> Cool, thanks!
>>
>> No problem! If you have doubts, please let me know.
> 
> Okay, so this looks slightly different than the outbound macro since it takes
> the register argument. In the case of outbound PCIE_GET_ATU_OUTB_UNR_REG_OFFSET
> returns the offset which was used like
> dw_pcie_write_dbi(pci, base, offset + reg, 0x4, val);
> 
> How should the value from PCIE_GET_ATU_INB_UNR_REG_ADDR be used?

My original way was this one:

+/* Register address builder */
+#define PCIE_GET_ATU_OUTB_UNR_REG_ADDR(region, register)		\
+					((0x3 << 20) | (region << 9) |	\
+					(register << 2))

Bjorn then converted to offset:

#define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region)  ((0x3 << 20) | (region << 9))

and applied the <<2 shift to the ATU registers.

So you can use:

#define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register)		\
					((0x3 << 20) | (region << 9) |	\
					(0x1 << 8)

Thanks.

> 
> Thanks
> Kishon
>

Thread

Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support Joao Pinto <Joao.Pinto@synopsys.com> - 2017-03-07 13:30 +0100
  Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support Joao Pinto <Joao.Pinto@synopsys.com> - 2017-03-08 12:40 +0100
    Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support Kishon Vijay Abraham I <kishon@ti.com> - 2017-03-08 12:50 +0100
      Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support Joao Pinto <Joao.Pinto@synopsys.com> - 2017-03-08 12:50 +0100
        Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support Joao Pinto <Joao.Pinto@synopsys.com> - 2017-03-08 16:40 +0100
          Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support Joao Pinto <Joao.Pinto@synopsys.com> - 2017-03-08 16:40 +0100
          Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support Christoph Hellwig <hch@infradead.org> - 2017-03-08 20:20 +0100
            Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support Joao Pinto <Joao.Pinto@synopsys.com> - 2017-03-09 13:00 +0100
        Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support Kishon Vijay Abraham I <kishon@ti.com> - 2017-03-08 17:10 +0100

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