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Re: [PATCH v2 0/7] Tegra210 clock bug fixes

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Series,

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>

On 02/23/2017 12:44 PM, Peter De Schrijver wrote:
> A number of bug fixes for the Tegra210 clock implementation.
>
> Changelog:
>
> v2: add better description for 'remove non-existing pll_m_out1 clock'
>
> Peter De Schrijver (7):
>   clk: tegra: fix pll_a1 iddq register, add pll_a1
>   clk: tegra: fix isp clock modelling
>   clk: tegra: correct afi parent
>   clk: tegra: remove non-existing pll_m_out1 clock
>   clk: tegra: don't warn for PLL defaults unnecessarily
>   clk: tegra: correct tegra210_pll_fixed_mdiv_cfg rate calculation
>   clk: tegra: fix type for m field
>
>  drivers/clk/tegra/clk-id.h               |  1 +
>  drivers/clk/tegra/clk-tegra-periph.c     | 13 +++++++++---
>  drivers/clk/tegra/clk-tegra210.c         | 35 ++++++++++++++++++++------------
>  drivers/clk/tegra/clk.h                  |  2 +-
>  include/dt-bindings/clock/tegra210-car.h |  4 ++--
>  5 files changed, 36 insertions(+), 19 deletions(-)
>

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[PATCH v2 0/7] Tegra210 clock bug fixes Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-02-23 12:00 +0100
  [PATCH v2 7/7] clk: tegra: fix type for m field Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-02-23 12:00 +0100
  [PATCH v2 1/7] clk: tegra: fix pll_a1 iddq register, add pll_a1 Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-02-23 12:00 +0100
  Re: [PATCH v2 0/7] Tegra210 clock bug fixes Mikko Perttunen <cyndis@kapsi.fi> - 2017-02-27 20:00 +0100

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