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Groups > linux.kernel > #1587584

[PATCH v4 15/23] drm/rockchip: dw-mipi-dsi: configure PHY before enabling

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The bias, bandgap and PLL should all be configured before we enable
them.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
---
v4:
- Add Sean's Reviewed-by
v3:
- Squash together two patches that both affect initialization order of
  the PHY
Unchanged in v2
---
 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index 78d676b7e516..4fee5176c606 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -413,12 +413,17 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 
 	dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
 
-	dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
 	dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div));
 	dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) |
 					 LOW_PROGRAM_EN);
 	dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
 					 HIGH_PROGRAM_EN);
+	dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
+
+	dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
+					 BIASEXTR_SEL(BIASEXTR_127_7));
+	dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
+					 BANDGAP_SEL(BANDGAP_96_10));
 
 	dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT |
 					 BIAS_BLOCK_ON | BANDGAP_ON);
@@ -429,10 +434,6 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 					 SETRD_MAX | POWER_MANAGE |
 					 TER_RESISTORS_ON);
 
-	dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
-					 BIASEXTR_SEL(BIASEXTR_127_7));
-	dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
-					 BANDGAP_SEL(BANDGAP_96_10));
 
 	dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf);
 	dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x55);
-- 
2.12.0.rc0.230.gf625d4cdb9.dirty

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[PATCH v4 00/23] drm/rockchip: MIPI fixes & improvements John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 18/23] drm/rockchip: dw-mipi-dsi: use specific poll helper John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 13/23] drm/rockchip: dw-mipi-dsi: fix escape clock rate John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 23/23] drm/rockchip: dw-mipi-dsi: add reset control John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 12/23] drm/rockchip: dw-mipi-dsi: allow commands in panel_disable John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 02/23] drm/rockchip: dw-mipi-dsi: pass mode in where needed John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 07/23] drm/rockchip: dw-mipi-dsi: include bad value in error message John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 21/23] drm/rockchip: dw-mipi-dsi: defer probe if panel is not loaded John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 19/23] drm/rockchip: dw-mipi-dsi: use positive check for N{H,V}SYNC John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 06/23] drm/rockchip: dw-mipi-dsi: avoid out-of-bounds read on tx_buf John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 15/23] drm/rockchip: dw-mipi-dsi: configure PHY before enabling John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 08/23] drm/rockchip: dw-mipi-dsi: respect message flags John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 04/23] drm/rockchip: dw-mipi-dsi: fix command header writes John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 10/23] drm/rockchip: dw-mipi-dsi: don't assume buffer is aligned John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 11/23] drm/rockchip: dw-mipi-dsi: prepare panel after phy init John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 17/23] drm/rockchip: dw-mipi-dsi: improve PLL configuration John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 09/23] drm/rockchip: dw-mipi-dsi: only request HS clock when required John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 03/23] drm/rockchip: dw-mipi-dsi: remove mode_set hook John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 05/23] drm/rockchip: dw-mipi-dsi: fix generic packet status check John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 01/23] drm/rockchip: dw-mipi-dsi: don't configure hardware in mode_set for MIPI John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 16/23] drm/rockchip: dw-mipi-dsi: properly configure PHY timing John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 22/23] drm/rockchip: dw-mipi-dsi: support non-burst modes John Keeping <john@metanate.com> - 2017-02-24 14:10 +0100
  Re: [PATCH v4 00/23] drm/rockchip: MIPI fixes & improvements Mark yao <mark.yao@rock-chips.com> - 2017-02-27 02:50 +0100
  Re: [PATCH v4 00/23] drm/rockchip: MIPI fixes & improvements Chris Zhong <zyw@rock-chips.com> - 2017-02-27 04:40 +0100

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