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Groups > linux.kernel > #1585473
| From | Will Deacon <will.deacon@arm.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH v2] arm64: cache: Skip an unnecessary data cache clean PoU operation |
| Date | 2017-02-21 17:00 +0100 |
| Message-ID | <tdl1a-4zS-55@gated-at.bofh.it> (permalink) |
| References | <t8HYl-5wK-1@gated-at.bofh.it> <tdkRr-4uK-15@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On Tue, Feb 21, 2017 at 03:47:27PM +0000, Catalin Marinas wrote:
> On Wed, Feb 08, 2017 at 03:19:37PM -0600, Shanker Donthineni wrote:
> > The cache management functions always do the data cache PoU
> > (point of unification) operations even though it is not required
> > on some systems. No need to clean data cache till PoU if all the
> > cache levels below PoUIS are WT (Write-Through) caches. It causes
> > a huge performance degradation when operating on a larger memory
> > area, especially THP with 64K page size kernel.
> >
> > For each online CPU, check the need of 'dc cvau' instruction and
> > update a global variable __dcache_flags. The two functions
> > __flush_cache_user_range() and __clean_dcache_area_pou() are
> > modified to skip an unnecessary code execution based on flags.
> > It won't change the existing behavior if any one of the online
> > CPU is capable of WB cache below PoUIS level.
> >
> > Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
> [...]
> > +#define CLIDR_LOUIS_SHIFT (21)
> > +#define CLIDR_LOUIS_MASK (0x7)
> > +#define CLIDR_LOUIS(x) (((x) >> CLIDR_LOUIS_SHIFT) & CLIDR_LOUIS_MASK)
>
> According to the ARMv8 ARM, CLIDR_EL1 "identifies the type of cache, or
> caches, that are implemented at each level and can be managed using the
> architected cache maintenance instructions that operate by set/way". The
> key part is "set/way" here and hence you cannot use CLIDR_EL1 and
> CCSIDR_EL1 to infer whether you can skip cache maintenance by VA.
>
> > + /* Go through all the cache level below LoUIS */
> > + for (lvl = 0; lvl < louis; lvl++) {
> > + csidr = cache_get_ccsidr(lvl << 1);
> > + if (csidr & CCSIDR_EL1_WRITE_BACK) {
>
> The type bits have also been deprecated in ARMv8 (we need to update the
> kernel or just remove the cache topology detection entirely, leaving it
> just to DT).
I'll dust off the patches I have for this...
Will
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Re: [PATCH v2] arm64: cache: Skip an unnecessary data cache clean PoU operation Catalin Marinas <catalin.marinas@arm.com> - 2017-02-21 16:50 +0100 Re: [PATCH v2] arm64: cache: Skip an unnecessary data cache clean PoU operation Will Deacon <will.deacon@arm.com> - 2017-02-21 17:00 +0100
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