Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]
Groups > linux.kernel > #1586427
| From | Andi Kleen <ak@linux.intel.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH] perf/x86: fix event counter update issue |
| Date | 2017-02-22 20:20 +0100 |
| Message-ID | <tdKCd-6rR-11@gated-at.bofh.it> (permalink) |
| References | (5 earlier) <sIXm1-4RO-3@gated-at.bofh.it> <sJVBv-3XH-11@gated-at.bofh.it> <sKYGZ-3jJ-19@gated-at.bofh.it> <tdGyD-3dk-37@gated-at.bofh.it> <tdHbj-3Iw-1@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
> No. It related to the counter width. The number of bits we can use should be > 1 bit less than the total width. Otherwise, there will be problem. > For big cores such as haswell, broadwell, skylake, the counter width is 48 bit. > So we can only use 47 bits. > For Silvermont and KNL, the counter width is only 32 bit I think. So we can only > use 31 bits. It is 40 bits on these cores, so 39bits. -Andi
Back to linux.kernel | Previous | Next — Previous in thread | Next in thread | Find similar | Unroll thread
Re: [PATCH] perf/x86: fix event counter update issue Vince Weaver <vincent.weaver@maine.edu> - 2017-02-22 16:00 +0100
RE: [PATCH] perf/x86: fix event counter update issue "Liang, Kan" <kan.liang@intel.com> - 2017-02-22 16:40 +0100
Re: [PATCH] perf/x86: fix event counter update issue Andi Kleen <ak@linux.intel.com> - 2017-02-22 20:20 +0100
RE: [PATCH] perf/x86: fix event counter update issue Vince Weaver <vincent.weaver@maine.edu> - 2017-02-23 16:10 +0100
RE: [PATCH] perf/x86: fix event counter update issue "Liang, Kan" <kan.liang@intel.com> - 2017-02-23 17:20 +0100
csiph-web