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Re: [patches] Re: [PATCH 1/9] RISC-V: Init and Halt Code

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On Tue, Jul 04, 2017 at 10:37:37PM +0200, Thomas Gleixner wrote:
> On Tue, 4 Jul 2017, Palmer Dabbelt wrote:

> > +unsigned long riscv_timebase;
> > +
> > +static int next_event(unsigned long delta, struct clock_event_device *ce)
> > +{
> > +	BUG_ON(ce != timer_riscv_device(smp_processor_id()));
> > +	sbi_set_timer(get_cycles64() + delta);
> > +	return 0;
> > +}
> > +
> > +static unsigned long long rdtime(struct clocksource *cs)
> > +{
> > +	BUG_ON(cs != timer_riscv_source(smp_processor_id()));
> > +	return get_cycles64();
> > +}
> > +
> > +void riscv_timer_interrupt(void)
> > +{
> > +	int cpu = smp_processor_id();
> > +	struct clock_event_device *evdev = timer_riscv_device(cpu);
> > +
> > +	evdev->event_handler(evdev);
> > +}
> > +
> > +void __init time_init(void)
> > +{
> > +	struct device_node *cpu;
> > +	u32 prop;
> > +	int cpu_id = smp_processor_id();
> > +
> > +	cpu = of_find_node_by_path("/cpus");
> > +	if (!cpu || of_property_read_u32(cpu, "timebase-frequency", &prop))
> > +		panic(KERN_WARNING "RISC-V system with no 'timebase-frequency' in DTS\n");
> > +	riscv_timebase = prop;
> > +
> > +	lpj_fine = riscv_timebase / HZ;
> > +
> > +	timer_riscv_init(cpu_id, riscv_timebase, &rdtime, &next_event);
> 
> This function is nowhere.... Neither can I find the header file.

It is part of the RISC-V clock driver patchset, please cf.
https://github.com/riscv/riscv-linux/commit/0705a31372d4714e54c5104e02021441785c1fd5

https://github.com/riscv/riscv-linux/commits/riscv-for-submission-v4
has the various RISC-V-related driver patchsets merged in (in
addition to this arch patchset).

Regards,
Karsten
-- 
Gem. Par. 28 Abs. 4 Bundesdatenschutzgesetz widerspreche ich der Nutzung
sowie der Weitergabe meiner personenbezogenen Daten für Zwecke der
Werbung sowie der Markt- oder Meinungsforschung.

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Thread

RISC-V Linux Port v4 Palmer Dabbelt <palmer@dabbelt.com> - 2017-07-04 22:00 +0200
  Re: [patches] Re: [PATCH 1/9] RISC-V: Init and Halt Code Karsten Merker <merker@debian.org> - 2017-07-04 23:20 +0200
    Re: [patches] Re: [PATCH 1/9] RISC-V: Init and Halt Code Thomas Gleixner <tglx@linutronix.de> - 2017-07-05 08:50 +0200
  Re: [patches] [PATCH 1/9] RISC-V: Init and Halt Code Jonathan Neuschäfer <j.neuschaefer@gmx.net> - 2017-07-05 00:00 +0200
    Re: [patches] [PATCH 1/9] RISC-V: Init and Halt Code Palmer Dabbelt <palmer@dabbelt.com> - 2017-07-07 00:40 +0200
      Re: [patches] [PATCH 1/9] RISC-V: Init and Halt Code Jonathan Neuschäfer <j.neuschaefer@gmx.net> - 2017-07-07 15:10 +0200
        Re: [patches] [PATCH 1/9] RISC-V: Init and Halt Code Palmer Dabbelt <palmer@dabbelt.com> - 2017-07-10 22:50 +0200
  Re: [PATCH 2/9] RISC-V: Atomic and Locking Code Peter Zijlstra <peterz@infradead.org> - 2017-07-05 10:50 +0200
    Re: [PATCH 2/9] RISC-V: Atomic and Locking Code Boqun Feng <boqun.feng@gmail.com> - 2017-07-06 06:20 +0200
      Re: [PATCH 2/9] RISC-V: Atomic and Locking Code Peter Zijlstra <peterz@infradead.org> - 2017-07-06 09:30 +0200
    Re: [PATCH 2/9] RISC-V: Atomic and Locking Code Palmer Dabbelt <palmer@dabbelt.com> - 2017-07-07 03:10 +0200
      Re: [PATCH 2/9] RISC-V: Atomic and Locking Code Boqun Feng <boqun.feng@gmail.com> - 2017-07-07 04:20 +0200
        Re: [PATCH 2/9] RISC-V: Atomic and Locking Code Palmer Dabbelt <palmer@dabbelt.com> - 2017-07-10 22:40 +0200
      Re: [PATCH 2/9] RISC-V: Atomic and Locking Code Peter Zijlstra <peterz@infradead.org> - 2017-07-07 10:10 +0200
        Re: [PATCH 2/9] RISC-V: Atomic and Locking Code Palmer Dabbelt <palmer@dabbelt.com> - 2017-07-10 22:40 +0200
  Re: [PATCH 8/9] RISC-V: User-facing API James Hogan <james.hogan@imgtec.com> - 2017-07-05 12:30 +0200
  Re: [PATCH 8/9] RISC-V: User-facing API Christoph Hellwig <hch@infradead.org> - 2017-07-06 04:10 +0200
    Re: [PATCH 8/9] RISC-V: User-facing API Will Deacon <will.deacon@arm.com> - 2017-07-06 11:00 +0200
      Re: [PATCH 8/9] RISC-V: User-facing API Christoph Hellwig <hch@infradead.org> - 2017-07-06 17:40 +0200
        Re: [PATCH 8/9] RISC-V: User-facing API Will Deacon <will.deacon@arm.com> - 2017-07-06 17:50 +0200
          Re: [PATCH 8/9] RISC-V: User-facing API Will Deacon <will.deacon@arm.com> - 2017-07-11 15:30 +0200
            Re: [PATCH 8/9] RISC-V: User-facing API Christoph Hellwig <hch@infradead.org> - 2017-07-11 16:00 +0200
              Re: [PATCH 8/9] RISC-V: User-facing API Palmer Dabbelt <palmer@dabbelt.com> - 2017-07-11 19:30 +0200
            Re: [PATCH 8/9] RISC-V: User-facing API Palmer Dabbelt <palmer@dabbelt.com> - 2017-07-11 19:10 +0200
  Re: [PATCH 2/9] RISC-V: Atomic and Locking Code Boqun Feng <boqun.feng@gmail.com> - 2017-07-06 05:40 +0200
  Re: [PATCH 8/9] RISC-V: User-facing API Dave P Martin <Dave.Martin@arm.com> - 2017-07-06 17:40 +0200
  Re: [patches] [PATCH 2/9] RISC-V: Atomic and Locking Code Jonathan Neuschäfer <j.neuschaefer@gmx.net> - 2017-07-07 15:20 +0200
    Re: [patches] [PATCH 2/9] RISC-V: Atomic and Locking Code Palmer Dabbelt <palmer@dabbelt.com> - 2017-07-10 22:50 +0200

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