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[PATCH v6 08/12] x86/ioapic: Refactor the delay logic in timer_irq_works()

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Kernel use timer_irq_works() to detects the timer IRQs. It calls
mdelay(10) to delay ten ticks and check whether the timer IRQ work
or not. The mdelay() depends on the loops_per_jiffy which is set up
in calibrate_delay(). Current kernel defaults the IRQ 0 is available
when it calibrates delay.

But it is wrong in the dump-capture kernel with 'notsc' option inherited
from 1st kernel option. dump-capture kernel can't make sure the timer IRQ
works well.

The correct design is making the interrupt mode setup and checking timer
IRQ works in advance of calibrate_delay(). That results in the mdelay()
being unusable in timer_irq_works().

Preparatory patch to make the setup in advance. Refactor the delay logic
by waiting for some cycles. In the system with X86_FEATURE_TSC feature,
Use rdtsc(), others will call __delay() directly.

Note: regard 4G as the max CPU frequence of current single CPU.

Signed-off-by: Dou Liyang <douly.fnst@cn.fujitsu.com>
---
 arch/x86/kernel/apic/io_apic.c | 45 ++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 43 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index 347bb9f..3087f0a 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -1607,6 +1607,43 @@ static int __init notimercheck(char *s)
 }
 __setup("no_timer_check", notimercheck);
 
+static void __init delay_with_tsc(void)
+{
+	unsigned long long start, now;
+	unsigned long end = jiffies + 4;
+
+	start = rdtsc();
+
+	/*
+	 * We don't know the TSC frequency yet, but waiting for
+	 * 40000000000/HZ TSC cycles is safe:
+	 * 4 GHz == 10 jiffies
+	 * 1 GHz == 40 jiffies
+	 */
+	do {
+		rep_nop();
+		now = rdtsc();
+	} while ((now - start) < 40000000000UL / HZ &&
+		time_before_eq(jiffies, end));
+}
+
+static void __init delay_without_tsc(void)
+{
+	unsigned long end = jiffies + 4;
+	int band = 1;
+
+	/*
+	 * We don't know any frequency yet, but waiting for
+	 * 40940000000/HZ cycles is safe:
+	 * 4 GHz == 10 jiffies
+	 * 1 GHz == 40 jiffies
+	 * 1 << 1 + 1 << 2 +...+ 1 << 11 = 4094
+	 */
+	do {
+		__delay(((1U << band++) * 10000000UL) / HZ);
+	} while (band < 12 && time_before_eq(jiffies, end));
+}
+
 /*
  * There is a nasty bug in some older SMP boards, their mptable lies
  * about the timer IRQ. We do the following to work around the situation:
@@ -1625,8 +1662,12 @@ static int __init timer_irq_works(void)
 
 	local_save_flags(flags);
 	local_irq_enable();
-	/* Let ten ticks pass... */
-	mdelay((10 * 1000) / HZ);
+
+	if (boot_cpu_has(X86_FEATURE_TSC))
+		delay_with_tsc();
+	else
+		delay_without_tsc();
+
 	local_irq_restore(flags);
 
 	/*
-- 
2.5.5

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[PATCH v6 00/12] Unify the interrupt delivery mode and do its setup in advance Dou Liyang <douly.fnst@cn.fujitsu.com> - 2017-07-03 13:10 +0200
  [PATCH v6 08/12] x86/ioapic: Refactor the delay logic in timer_irq_works() Dou Liyang <douly.fnst@cn.fujitsu.com> - 2017-07-03 13:10 +0200
  [PATCH v6 05/12] x86/apic: Unify interrupt mode setup for SMP-capable system Dou Liyang <douly.fnst@cn.fujitsu.com> - 2017-07-03 13:10 +0200
  [PATCH v6 10/12] x86/xen: Bypass intr mode setup in enlighten_pv system Dou Liyang <douly.fnst@cn.fujitsu.com> - 2017-07-03 13:10 +0200
  [PATCH v6 04/12] x86/apic: Move logical APIC ID away from apic_bsp_setup() Dou Liyang <douly.fnst@cn.fujitsu.com> - 2017-07-03 13:10 +0200
  [PATCH v6 01/12] x86/apic: Construct a selector for the interrupt delivery mode Dou Liyang <douly.fnst@cn.fujitsu.com> - 2017-07-03 13:20 +0200
  [PATCH v6 06/12] x86/apic: Mark the apic_intr_mode extern for sanity check cleanup Dou Liyang <douly.fnst@cn.fujitsu.com> - 2017-07-03 13:20 +0200
  [PATCH v6 03/12] x86/apic: Split local APIC timer setup from the APIC setup Dou Liyang <douly.fnst@cn.fujitsu.com> - 2017-07-03 13:20 +0200
  [PATCH v6 09/12] x86/init: add intr_mode_init to x86_init_ops Dou Liyang <douly.fnst@cn.fujitsu.com> - 2017-07-03 13:20 +0200

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