Re: [PATCH 4/9] clk: imx: add pllv4 support

From	Stephen Boyd <sboyd@codeaurora.org>
Newsgroups	linux.kernel
Subject	Re: [PATCH 4/9] clk: imx: add pllv4 support
Date	2017-07-01 02:40 +0200
Message-ID	<tYeC6-42w-27@gated-at.bofh.it> (permalink)
References	<tRNOi-4yK-11@gated-at.bofh.it> <tUgCv-27M-55@gated-at.bofh.it> <tUgCv-27M-53@gated-at.bofh.it> <tUnNG-6PZ-69@gated-at.bofh.it>
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On 06/20, Dong Aisheng wrote:
> On Mon, Jun 19, 2017 at 06:59:17PM -0700, Stephen Boyd wrote:
> > On 05/15, Dong Aisheng wrote:
> > > +
> > > +	if (clk_pllv4_is_enabled(hw)) {
> > > +		WARN(1, "clk_pllv4: can't change rate when pll is enabled");
> > > +		return -EINVAL;
> > 
> > Sad, CLK_SET_RATE_GATE isn't working for you I suppose?
> > 
> 
> CLK_SET_RATE_GATE can't work in early stage before running clk_disable_unused.
> At that point, the clock tree state is still not consistent with HW.
> e.g. prepare/enable count is still zero but it's actually enabled due to
> reset state or bootloader.
> 
> The code here is adding a double check in case user sets rate in early stage.
> 
> However, probably it could also be moved into clock core as it's not platform
> dependant behavior?
> 

Ok. It would be good to fix the core framework to synchronize the
prepared/enabled state at registration time so we don't need this
check in the driver.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Thread

Re: [PATCH 4/9] clk: imx: add pllv4 support Stephen Boyd <sboyd@codeaurora.org> - 2017-06-20 04:00 +0200
  Re: [PATCH 4/9] clk: imx: add pllv4 support Dong Aisheng <dongas86@gmail.com> - 2017-06-20 11:40 +0200
    Re: [PATCH 4/9] clk: imx: add pllv4 support Stephen Boyd <sboyd@codeaurora.org> - 2017-07-01 02:40 +0200
      RE: [PATCH 4/9] clk: imx: add pllv4 support "A.s. Dong" <aisheng.dong@nxp.com> - 2017-07-03 05:30 +0200

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