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[PATCH 1/4] ARM: aspeed: g4: Add USB functions to pinctrl bindings

From Andrew Jeffery <andrew@aj.id.au>
Newsgroups linux.kernel
Subject [PATCH 1/4] ARM: aspeed: g4: Add USB functions to pinctrl bindings
Date 2017-06-27 04:20 +0200
Message-ID <tWOgF-2mL-5@gated-at.bofh.it> (permalink)
References <tWOgF-2mL-1@gated-at.bofh.it>
Organization linux.* mail to news gateway

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The AST2400 contains several USB controllers:

* USB 1.1 Host Controller
* USB 2.0 Host Controller
* Combined USB 2.0 Virtual Hub and USB 1.1 HID Controller

Pins for three ports are routed to the three controllers such that:

* Port 1 is a dedicated USB 1.1 host port
* Port 2 is shared between the USB 1.1 host and HID controllers
* Port 3 is shared between the USB 2.0 host and Hub controllers

As the pins for port 1 are fixed function there is no associated mux
function or group described in the bindings. Ports 2 and 3 are muxed as
above, and the table below describes the mapping between pinmux function
names and ports:

Port  | USB Version  | USB Mode  | Mux Function
------|--------------|-----------|-------------
1     | 1.1          | Host      | -
2     | 1.1          | Host      | USB11H2
2     | 1.1          | Device    | USB11D1
3     | 2.0          | Host      | USB2H1
3     | 2.0          | Device    | USB2D1

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
 Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
index ca01710ee29a..09142dab47db 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
@@ -69,8 +69,9 @@ PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RGMII1 RGMII2 RMII1 RMII2 ROM16 ROM8 ROMCS1
 ROMCS2 ROMCS3 ROMCS4 RXD1 RXD2 RXD3 RXD4 SALT1 SALT2 SALT3 SALT4 SD1 SD2 SGPMCK
 SGPMI SGPMLD SGPMO SGPSCK SGPSI0 SGPSI1 SGPSLD SIOONCTRL SIOPBI SIOPBO SIOPWREQ
 SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1DEBUG SPI1PASSTHRU SPICS1 TIMER3 TIMER4
-TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 TXD3 TXD4 UART6 USBCKI VGABIOS_ROM VGAHS
-VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1 WDTRST2
+TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 TXD3 TXD4 UART6 USB11D1 USB11H2 USB2D1
+USB2H1 USBCKI VGABIOS_ROM VGAHS VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1
+WDTRST2
 
 aspeed,ast2500-pinctrl, aspeed,g5-pinctrl:
 
-- 
2.11.0

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Thread

[PATCH 0/4] pinctrl: Add USB support for Aspeed SoCs Andrew Jeffery <andrew@aj.id.au> - 2017-06-27 04:20 +0200
  [PATCH 2/4] ARM: aspeed: g5: Add USB functions to pinctrl bindings Andrew Jeffery <andrew@aj.id.au> - 2017-06-27 04:20 +0200
    Re: [PATCH 2/4] ARM: aspeed: g5: Add USB functions to pinctrl  bindings Rob Herring <robh@kernel.org> - 2017-06-29 22:20 +0200
      Re: [PATCH 2/4] ARM: aspeed: g5: Add USB functions to pinctrl  bindings Rob Herring <robh@kernel.org> - 2017-06-29 22:40 +0200
        Re: [PATCH 2/4] ARM: aspeed: g5: Add USB functions to pinctrl  bindings Andrew Jeffery <andrew@aj.id.au> - 2017-06-30 03:30 +0200
  [PATCH 1/4] ARM: aspeed: g4: Add USB functions to pinctrl bindings Andrew Jeffery <andrew@aj.id.au> - 2017-06-27 04:20 +0200
    Re: [PATCH 1/4] ARM: aspeed: g4: Add USB functions to pinctrl  bindings Benjamin Herrenschmidt <benh@kernel.crashing.org> - 2017-06-27 06:00 +0200
      Re: [PATCH 1/4] ARM: aspeed: g4: Add USB functions to pinctrl  bindings Andrew Jeffery <andrew@aj.id.au> - 2017-06-30 03:30 +0200
    Re: [PATCH 1/4] ARM: aspeed: g4: Add USB functions to pinctrl  bindings Rob Herring <robh@kernel.org> - 2017-06-29 22:20 +0200
  [PATCH 4/4] pinctrl: aspeed: g5: Add USB device and host support Andrew Jeffery <andrew@aj.id.au> - 2017-06-27 04:20 +0200
  [PATCH 3/4] pinctrl: aspeed: g4: Add USB device and host support Andrew Jeffery <andrew@aj.id.au> - 2017-06-27 04:20 +0200
  Re: [PATCH 0/4] pinctrl: Add USB support for Aspeed SoCs Linus Walleij <linus.walleij@linaro.org> - 2017-06-29 15:00 +0200
    Re: [PATCH 0/4] pinctrl: Add USB support for Aspeed SoCs Andrew Jeffery <andrew@aj.id.au> - 2017-06-30 03:30 +0200

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