Re: [PATCHv7 13/14] x86: Enable 5-level paging support

From	Ingo Molnar <mingo@kernel.org>
Newsgroups	linux.kernel
Subject	Re: [PATCHv7 13/14] x86: Enable 5-level paging support
Date	2017-06-22 11:30 +0200
Message-ID	<tV6B4-2JO-13@gated-at.bofh.it> (permalink)
References	<tPl05-8cX-3@gated-at.bofh.it> <tPl06-8cX-5@gated-at.bofh.it>
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* Kirill A. Shutemov <kirill.shutemov@linux.intel.com> wrote:

> Most of things are in place and we can enable support of 5-level paging.
> 
> The patch makes XEN_PV dependent on !X86_5LEVEL. XEN_PV is not ready to
> work with 5-level paging.

Please make a short comment about that in the Kconfig code as well, instead of a 
silent, undocumented 'depends' clause.

>  config PGTABLE_LEVELS
>  	int
> +	default 5 if X86_5LEVEL
>  	default 4 if X86_64
>  	default 3 if X86_PAE
>  	default 2
> @@ -1390,6 +1391,10 @@ config X86_PAE
>  	  has the cost of more pagetable lookup overhead, and also
>  	  consumes more pagetable space per process.
>  
> +config X86_5LEVEL
> +	bool "Enable 5-level page tables support"
> +	depends on X86_64

So since users will be enabling it, this needs a proper help text that explains 
what hardware supports it ("future Intel CPUs" will do if models are not public 
yet), a short blurb about what it's good for - and a link to the Documentation/ 
file explaining it all.

Thanks,

	Ingo

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Re: [PATCHv7 13/14] x86: Enable 5-level paging support Ingo Molnar <mingo@kernel.org> - 2017-06-22 11:30 +0200

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