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[PATCH v2 03/17] clk: ingenic: support PLLs with no bypass bit

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The second PLL of the JZ4770 does not have a bypass bit.
This commit makes it possible to support it with the current common CGU
code.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
 drivers/clk/ingenic/cgu.c | 3 ++-
 drivers/clk/ingenic/cgu.h | 2 ++
 2 files changed, 4 insertions(+), 1 deletion(-)

 v2: No change

diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c
index eb9002ccf3fc..75b083ba294c 100644
--- a/drivers/clk/ingenic/cgu.c
+++ b/drivers/clk/ingenic/cgu.c
@@ -100,7 +100,8 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 	n += pll_info->n_offset;
 	od_enc = ctl >> pll_info->od_shift;
 	od_enc &= GENMASK(pll_info->od_bits - 1, 0);
-	bypass = !!(ctl & BIT(pll_info->bypass_bit));
+	bypass = !pll_info->no_bypass_bit &&
+		 !!(ctl & BIT(pll_info->bypass_bit));
 	enable = !!(ctl & BIT(pll_info->enable_bit));
 
 	if (bypass)
diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h
index da448b0cac18..21420b455985 100644
--- a/drivers/clk/ingenic/cgu.h
+++ b/drivers/clk/ingenic/cgu.h
@@ -48,6 +48,7 @@
  * @bypass_bit: the index of the bypass bit in the PLL control register
  * @enable_bit: the index of the enable bit in the PLL control register
  * @stable_bit: the index of the stable bit in the PLL control register
+ * @no_bypass_bit: if set, the PLL has no bypass functionality
  */
 struct ingenic_cgu_pll_info {
 	unsigned reg;
@@ -58,6 +59,7 @@ struct ingenic_cgu_pll_info {
 	u8 bypass_bit;
 	u8 enable_bit;
 	u8 stable_bit;
+	bool no_bypass_bit;
 };
 
 /**
-- 
2.11.0

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[PATCH v2 01/17] clk: ingenic: Use const pointer to clk_ops in struct Paul Cercueil <paul@crapouillou.net> - 2017-06-20 17:30 +0200
  [PATCH v2 08/17] serial: 8250_ingenic: Parse earlycon options Paul Cercueil <paul@crapouillou.net> - 2017-06-20 17:30 +0200
  [PATCH v2 15/17] MIPS: JZ4770: Workaround for corrupted DMA transfers Paul Cercueil <paul@crapouillou.net> - 2017-06-20 17:30 +0200
    Re: [PATCH v2 15/17] MIPS: JZ4770: Workaround for corrupted DMA  transfers Marcin Nowakowski <marcin.nowakowski@imgtec.com> - 2017-06-22 09:30 +0200
      Re: [PATCH v2 15/17] MIPS: JZ4770: Workaround for corrupted DMA  transfers Paul Cercueil <paul@crapouillou.net> - 2017-06-26 15:40 +0200
  [PATCH v2 03/17] clk: ingenic: support PLLs with no bypass bit Paul Cercueil <paul@crapouillou.net> - 2017-06-20 17:30 +0200
  [PATCH v2 07/17] serial: 8250_ingenic: Add support for the JZ4770 SoC Paul Cercueil <paul@crapouillou.net> - 2017-06-20 17:30 +0200
  [PATCH v2 06/17] serial: core: Make uart_parse_options take const char* argument Paul Cercueil <paul@crapouillou.net> - 2017-06-20 17:30 +0200
  [PATCH v2 05/17] clk: Add Ingenic jz4770 CGU driver Paul Cercueil <paul@crapouillou.net> - 2017-06-20 17:30 +0200
  [PATCH v2 16/17] devicetree/bindings: Add GCW vendor prefix Paul Cercueil <paul@crapouillou.net> - 2017-06-20 17:30 +0200
  Re: [PATCH v2 01/17] clk: ingenic: Use const pointer to clk_ops in  struct Stephen Boyd <sboyd@codeaurora.org> - 2017-06-22 00:00 +0200
    Re: [PATCH v2 01/17] clk: ingenic: Use const pointer to clk_ops in  struct Paul Cercueil <paul@crapouillou.net> - 2017-06-26 15:50 +0200

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