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Groups > linux.kernel > #1670088
| From | Stephen Boyd <sboyd@codeaurora.org> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCHv2] clk: socfpga: Fix the smplsel on Arria10 and Stratix10 |
| Date | 2017-06-20 02:10 +0200 |
| Message-ID | <tUeU3-1fU-63@gated-at.bofh.it> (permalink) |
| References | <tQ6s2-5m5-15@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On 06/08, Dinh Nguyen wrote:
> The smplsel bits for the SDMMC clock on Arria10 and Stratix10 platforms are
> offset by 1 additional bit.
>
> Add a new macro SYSMGR_SDMMC_CTRL_SET_AS10 for usage on the Arria10 and
> Stratix10 platforms.
>
> Fixes: 5611a5ba8e54 ("clk: socfpga: update clk.h so for Arria10 platform to use")
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> ---
Applied to clk-next
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[PATCHv2] clk: socfpga: Fix the smplsel on Arria10 and Stratix10 Dinh Nguyen <dinguyen@kernel.org> - 2017-06-08 16:20 +0200 Re: [PATCHv2] clk: socfpga: Fix the smplsel on Arria10 and Stratix10 Stephen Boyd <sboyd@codeaurora.org> - 2017-06-20 02:10 +0200
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