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Re: [PATCH v2 00/10] PCID and improved laziness

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On Sun, Jun 18, 2017 at 2:29 PM, Levin, Alexander (Sasha Levin)
<alexander.levin@verizon.com> wrote:
> On Tue, Jun 13, 2017 at 09:56:18PM -0700, Andy Lutomirski wrote:
>>There are three performance benefits here:
>>
>>1. TLB flushing is slow.  (I.e. the flush itself takes a while.)
>>   This avoids many of them when switching tasks by using PCID.  In
>>   a stupid little benchmark I did, it saves about 100ns on my laptop
>>   per context switch.  I'll try to improve that benchmark.
>>
>>2. Mms that have been used recently on a given CPU might get to keep
>>   their TLB entries alive across process switches with this patch
>>   set.  TLB fills are pretty fast on modern CPUs, but they're even
>>   faster when they don't happen.
>>
>>3. Lazy TLB is way better.  We used to do two stupid things when we
>>   ran kernel threads: we'd send IPIs to flush user contexts on their
>>   CPUs and then we'd write to CR3 for no particular reason as an excuse
>>   to stop further IPIs.  With this patch, we do neither.
>>
>>This will, in general, perform suboptimally if paravirt TLB flushing
>>is in use (currently just Xen, I think, but Hyper-V is in the works).
>>The code is structured so we could fix it in one of two ways: we
>>could take a spinlock when touching the percpu state so we can update
>>it remotely after a paravirt flush, or we could be more careful about
>>our exactly how we access the state and use cmpxchg16b to do atomic
>>remote updates.  (On SMP systems without cmpxchg16b, we'd just skip
>>the optimization entirely.)
>
> Hey Andy,
>
> I've started seeing the following in -next:
>
> ------------[ cut here ]------------
> kernel BUG at arch/x86/mm/tlb.c:47!

...

> Call Trace:
>  flush_tlb_func_local arch/x86/mm/tlb.c:239 [inline]
>  flush_tlb_mm_range+0x26d/0x370 arch/x86/mm/tlb.c:317
>  flush_tlb_page arch/x86/include/asm/tlbflush.h:253 [inline]

I think I see what's going on, and it should be fixed in the PCID
series.  I'll split out the fix.

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[PATCH v2 00/10] PCID and improved laziness Andy Lutomirski <luto@kernel.org> - 2017-06-14 07:00 +0200
  [PATCH v2 09/10] x86/mm: Enable CR4.PCIDE on supported systems Andy Lutomirski <luto@kernel.org> - 2017-06-14 07:00 +0200
    Re: [PATCH v2 09/10] x86/mm: Enable CR4.PCIDE on supported systems Juergen Gross <jgross@suse.com> - 2017-06-14 07:40 +0200
  [PATCH v2 06/10] x86/mm: Stop calling leave_mm() in idle code Andy Lutomirski <luto@kernel.org> - 2017-06-14 07:00 +0200
  [PATCH v2 04/10] x86/mm: Track the TLB's tlb_gen and update the flushing algorithm Andy Lutomirski <luto@kernel.org> - 2017-06-14 07:00 +0200
  [PATCH v2 02/10] x86/mm: Remove reset_lazy_tlbstate() Andy Lutomirski <luto@kernel.org> - 2017-06-14 07:00 +0200
    Re: [PATCH v2 02/10] x86/mm: Remove reset_lazy_tlbstate() Rik van Riel <riel@redhat.com> - 2017-06-15 21:30 +0200
  [PATCH v2 10/10] x86/mm: Try to preserve old TLB entries using PCID Andy Lutomirski <luto@kernel.org> - 2017-06-14 07:00 +0200
    Re: [PATCH v2 10/10] x86/mm: Try to preserve old TLB entries using  PCID Nadav Amit <nadav.amit@gmail.com> - 2017-06-18 08:30 +0200
      Re: [PATCH v2 10/10] x86/mm: Try to preserve old TLB entries using PCID Andy Lutomirski <luto@kernel.org> - 2017-06-20 00:10 +0200
  Re: [PATCH v2 00/10] PCID and improved laziness Dave Hansen <dave.hansen@intel.com> - 2017-06-15 00:20 +0200
    Re: [PATCH v2 00/10] PCID and improved laziness Andy Lutomirski <luto@kernel.org> - 2017-06-15 00:50 +0200
  Re: [PATCH v2 00/10] PCID and improved laziness "Levin, Alexander (Sasha Levin)" <alexander.levin@verizon.com> - 2017-06-18 23:40 +0200
    Re: [PATCH v2 00/10] PCID and improved laziness Andy Lutomirski <luto@kernel.org> - 2017-06-19 06:50 +0200

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