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Re: [HMM-CDM 0/5] Cache coherent device memory (CDM) with HMM

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On 06/14/2017 01:11 PM, Jérôme Glisse wrote:
> Cache coherent device memory apply to architecture with system bus
> like CAPI or CCIX. Device connected to such system bus can expose
> their memory to the system and allow cache coherent access to it
> from the CPU.

How does this interact with device memory that's enumerated in the new
ACPI 6.2 HMAT?  That stuff is also in the normal e820 and, by default,
treated as normal system RAM.  Would this mechanism be used for those
devices as well?

http://www.uefi.org/sites/default/files/resources/ACPI_6_2.pdf

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[HMM-CDM 0/5] Cache coherent device memory (CDM) with HMM Jérôme Glisse <jglisse@redhat.com> - 2017-06-14 22:20 +0200
  Re: [HMM-CDM 0/5] Cache coherent device memory (CDM) with HMM Dave Hansen <dave.hansen@intel.com> - 2017-06-14 23:30 +0200
    Re: [HMM-CDM 0/5] Cache coherent device memory (CDM) with HMM Jerome Glisse <jglisse@redhat.com> - 2017-06-14 23:40 +0200
      Re: [HMM-CDM 0/5] Cache coherent device memory (CDM) with HMM Dave Hansen <dave.hansen@intel.com> - 2017-06-15 00:00 +0200
        Re: [HMM-CDM 0/5] Cache coherent device memory (CDM) with HMM Benjamin Herrenschmidt <benh@kernel.crashing.org> - 2017-06-15 00:10 +0200
        Re: [HMM-CDM 0/5] Cache coherent device memory (CDM) with HMM Balbir Singh <bsingharora@gmail.com> - 2017-06-15 01:50 +0200

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