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[PATCH 15/15] spi: qup: support for qup v1 dma

From Varadarajan Narayanan <varada@codeaurora.org>
Newsgroups linux.kernel
Subject [PATCH 15/15] spi: qup: support for qup v1 dma
Date 2017-06-16 11:10 +0200
Message-ID <tSVqs-6tS-57@gated-at.bofh.it> (permalink)
References <tSVgJ-6bj-7@gated-at.bofh.it>
Organization linux.* mail to news gateway

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Currently the QUP Version v1 does not work with DMA so added
the support for the same.

1. It uses ADM DMA which requires TX and RX CRCI
2. DMA channel initialization need to be done after setting
   block size for having valid values in maxburst
3. QUP mode should be DMOV instead of BAM.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
---
 .../devicetree/bindings/spi/qcom,spi-qup.txt       |  6 ++++
 drivers/spi/spi-qup.c                              | 35 +++++++++++++++++-----
 2 files changed, 34 insertions(+), 7 deletions(-)

diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
index 5c09077..e754181 100644
--- a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
+++ b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
@@ -38,6 +38,12 @@ Optional properties:
 - dma-names:    Names for the dma channels, if present. There must be at
                 least one channel named "tx" for transmit and named "rx" for
                 receive.
+- qcom,tx-crci: Identificator for Client Rate Control Interface (CRCI) to be
+		used with TX DMA channel. Required when using DMA for
+		transmission with QUP Version 1 i.e qcom,spi-qup-v1.1.1.
+- qcom,rx-crci: Identificator for Client Rate Control Interface (CRCI) to be
+		used with RX DMA channel. Required when using DMA for
+		receiving with QUP Version 1 i.e qcom,spi-qup-v1.1.1.
 
 SPI slave nodes must be children of the SPI master node and can contain
 properties described in Documentation/devicetree/bindings/spi/spi-bus.txt
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index 5455b0c..88ca10b 100644
--- a/drivers/spi/spi-qup.c
+++ b/drivers/spi/spi-qup.c
@@ -657,7 +657,8 @@ static int spi_qup_io_prep(struct spi_device *spi, struct spi_transfer *xfer)
 	else if (spi->master->can_dma &&
 		 spi->master->can_dma(spi->master, spi, xfer) &&
 		 spi->master->cur_msg_mapped)
-		controller->mode = QUP_IO_M_MODE_BAM;
+		controller->mode = controller->qup_v1 ? QUP_IO_M_MODE_DMOV :
+							QUP_IO_M_MODE_BAM;
 	else
 		controller->mode = QUP_IO_M_MODE_BLOCK;
 
@@ -696,6 +697,7 @@ static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
 		writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
 		break;
 	case QUP_IO_M_MODE_BAM:
+	case QUP_IO_M_MODE_DMOV:
 		reinit_completion(&controller->txc);
 		reinit_completion(&controller->rxc);
 		writel_relaxed(controller->n_words,
@@ -900,6 +902,7 @@ static int spi_qup_init_dma(struct spi_master *master, resource_size_t base)
 	struct dma_slave_config *rx_conf = &spi->rx_conf,
 				*tx_conf = &spi->tx_conf;
 	struct device *dev = spi->dev;
+	u32 tx_crci = 0, rx_crci = 0;
 	int ret;
 
 	/* allocate dma resources, if available */
@@ -913,16 +916,34 @@ static int spi_qup_init_dma(struct spi_master *master, resource_size_t base)
 		goto err_tx;
 	}
 
+	if (spi->qup_v1) {
+		ret = of_property_read_u32(dev->of_node, "qcom,tx-crci",
+					   &tx_crci);
+		if (ret) {
+			dev_err(dev, "missing property qcom,tx-crci\n");
+			goto err;
+		}
+
+		ret = of_property_read_u32(dev->of_node, "qcom,rx-crci",
+					   &rx_crci);
+		if (ret) {
+			dev_err(dev, "missing property qcom,rx-crci\n");
+			goto err;
+		}
+	}
+
 	/* set DMA parameters */
 	rx_conf->direction = DMA_DEV_TO_MEM;
 	rx_conf->device_fc = 1;
 	rx_conf->src_addr = base + QUP_INPUT_FIFO;
 	rx_conf->src_maxburst = spi->in_blk_sz;
+	rx_conf->slave_id = rx_crci;
 
 	tx_conf->direction = DMA_MEM_TO_DEV;
 	tx_conf->device_fc = 1;
 	tx_conf->dst_addr = base + QUP_OUTPUT_FIFO;
 	tx_conf->dst_maxburst = spi->out_blk_sz;
+	tx_conf->slave_id = tx_crci;
 
 	ret = dmaengine_slave_config(master->dma_rx, rx_conf);
 	if (ret) {
@@ -1049,12 +1070,6 @@ static int spi_qup_probe(struct platform_device *pdev)
 	controller->cclk = cclk;
 	controller->irq = irq;
 
-	ret = spi_qup_init_dma(master, res->start);
-	if (ret == -EPROBE_DEFER)
-		goto error;
-	else if (!ret)
-		master->can_dma = spi_qup_can_dma;
-
 	/* set v1 flag if device is version 1 */
 	if (of_device_is_compatible(dev->of_node, "qcom,spi-qup-v1.1.1"))
 		controller->qup_v1 = 1;
@@ -1091,6 +1106,12 @@ static int spi_qup_probe(struct platform_device *pdev)
 		 controller->in_blk_sz, controller->in_fifo_sz,
 		 controller->out_blk_sz, controller->out_fifo_sz);
 
+	ret = spi_qup_init_dma(master, res->start);
+	if (ret == -EPROBE_DEFER)
+		goto error;
+	else if (!ret)
+		master->can_dma = spi_qup_can_dma;
+
 	writel_relaxed(1, base + QUP_SW_RESET);
 
 	ret = spi_qup_set_state(controller, QUP_STATE_RESET);
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

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Thread

[PATCH 00/15] spi: qup: Fixes and add support for >64k transfers Varadarajan Narayanan <varada@codeaurora.org> - 2017-06-16 11:00 +0200
  [PATCH 03/15] spi: qup: Add completion timeout for dma mode Varadarajan Narayanan <varada@codeaurora.org> - 2017-06-16 11:00 +0200
  [PATCH 02/15] spi: qup: Setup DMA mode correctly Varadarajan Narayanan <varada@codeaurora.org> - 2017-06-16 11:10 +0200
  [PATCH 13/15] spi: qup: allow multiple DMA transactions per spi xfer Varadarajan Narayanan <varada@codeaurora.org> - 2017-06-16 11:10 +0200
  [PATCH 06/15] spi: qup: Fix error handling in spi_qup_prep_sg Varadarajan Narayanan <varada@codeaurora.org> - 2017-06-16 11:10 +0200
  [PATCH 14/15] spi: qup: Ensure done detection Varadarajan Narayanan <varada@codeaurora.org> - 2017-06-16 11:10 +0200
  [PATCH 09/15] spi: qup: refactor spi_qup_io_config into two functions Varadarajan Narayanan <varada@codeaurora.org> - 2017-06-16 11:10 +0200
  [PATCH 12/15] spi: qup: refactor spi_qup_prep_sg Varadarajan Narayanan <varada@codeaurora.org> - 2017-06-16 11:10 +0200
  [PATCH 10/15] spi: qup: call io_config in mode specific function Varadarajan Narayanan <varada@codeaurora.org> - 2017-06-16 11:10 +0200
  [PATCH 07/15] spi: qup: Fix transaction done signaling Varadarajan Narayanan <varada@codeaurora.org> - 2017-06-16 11:10 +0200
  [PATCH 04/15] spi: qup: Add completion timeout for fifo/block mode Varadarajan Narayanan <varada@codeaurora.org> - 2017-06-16 11:10 +0200
  [PATCH 05/15] spi: qup: Place the QUP in run mode before DMA transactions Varadarajan Narayanan <varada@codeaurora.org> - 2017-06-16 11:10 +0200
  [PATCH 08/15] spi: qup: Do block sized read/write in block mode Varadarajan Narayanan <varada@codeaurora.org> - 2017-06-16 11:10 +0200
  [PATCH 15/15] spi: qup: support for qup v1 dma Varadarajan Narayanan <varada@codeaurora.org> - 2017-06-16 11:10 +0200
  [PATCH 11/15] spi: qup: allow block mode to generate multiple transactions Varadarajan Narayanan <varada@codeaurora.org> - 2017-06-16 11:10 +0200
  [PATCH 01/15] spi: qup: Enable chip select support Varadarajan Narayanan <varada@codeaurora.org> - 2017-06-16 11:10 +0200

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