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Groups > linux.kernel > #1661384
| From | Noam Camus <noamca@mellanox.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH 11/11] ARC: [plat-eznps] avoid toggling of DPC register |
| Date | 2017-06-08 17:30 +0200 |
| Message-ID | <tQ7xM-60p-27@gated-at.bofh.it> (permalink) |
| References | <tQ7xL-60p-3@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
From: Elad Kanfi <eladkan@mellanox.com> HW bug description: in case of HW thread context switch the dpc configuration of the exiting thread is dragged one cycle into the next thread. In order to avoid the consequences of this bug, the DPC register is set to an initial value, and not changed afterwards. Signed-off-by: Elad Kanfi <eladkan@mellanox.com> Signed-off-by: Noam Camus <noamca@mellanox.com> --- arch/arc/plat-eznps/include/plat/ctop.h | 1 + arch/arc/plat-eznps/mtm.c | 12 ++++++++++++ 2 files changed, 13 insertions(+), 0 deletions(-) diff --git a/arch/arc/plat-eznps/include/plat/ctop.h b/arch/arc/plat-eznps/include/plat/ctop.h index 7729d3d..0c7d110 100644 --- a/arch/arc/plat-eznps/include/plat/ctop.h +++ b/arch/arc/plat-eznps/include/plat/ctop.h @@ -39,6 +39,7 @@ #define CTOP_AUX_LOGIC_CORE_ID (CTOP_AUX_BASE + 0x018) #define CTOP_AUX_MT_CTRL (CTOP_AUX_BASE + 0x020) #define CTOP_AUX_HW_COMPLY (CTOP_AUX_BASE + 0x024) +#define CTOP_AUX_DPC (CTOP_AUX_BASE + 0x02C) #define CTOP_AUX_LPC (CTOP_AUX_BASE + 0x030) #define CTOP_AUX_EFLAGS (CTOP_AUX_BASE + 0x080) #define CTOP_AUX_IACK (CTOP_AUX_BASE + 0x088) diff --git a/arch/arc/plat-eznps/mtm.c b/arch/arc/plat-eznps/mtm.c index f77335a..3c7dec9 100644 --- a/arch/arc/plat-eznps/mtm.c +++ b/arch/arc/plat-eznps/mtm.c @@ -101,6 +101,18 @@ void mtm_enable_core(unsigned int cpu) int i; struct nps_host_reg_aux_mt_ctrl mt_ctrl; struct nps_host_reg_mtm_cfg mtm_cfg; + struct nps_host_reg_aux_dpc dpc; + + /* + * Initializing dpc register in each CPU. + * Overwriting the init value of the DPC + * register so that CMEM and FMT virtual address + * spaces are accessible, and Data Plane HW + * facilities are enabled. + */ + dpc.ien = 1; + dpc.men = 1; + write_aux_reg(CTOP_AUX_DPC, dpc.value); if (NPS_CPU_TO_THREAD_NUM(cpu) != 0) return; -- 1.7.1
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[PATCH 00/11] plat-eznps upstream cont. set 2 Noam Camus <noamca@mellanox.com> - 2017-06-08 17:30 +0200 [PATCH 05/11] ARC: Support more than one PGDIR for KVADDR Noam Camus <noamca@mellanox.com> - 2017-06-08 17:30 +0200 [PATCH 01/11] ARC: set level of log per CPU during boot to be debug level Noam Camus <noamca@mellanox.com> - 2017-06-08 17:30 +0200 [PATCH 02/11] ARC: send ipi to all cpus sharing task mm in case of page fault Noam Camus <noamca@mellanox.com> - 2017-06-08 17:30 +0200 [PATCH 11/11] ARC: [plat-eznps] avoid toggling of DPC register Noam Camus <noamca@mellanox.com> - 2017-06-08 17:30 +0200 [PATCH 04/11] ARC: Add CPU topology Noam Camus <noamca@mellanox.com> - 2017-06-08 17:30 +0200 [PATCH 03/11] ARC: Allow irq threading Noam Camus <noamca@mellanox.com> - 2017-06-08 17:30 +0200 [PATCH 10/11] ARC: [plat-eznps] handle dedicated AUX registers Noam Camus <noamca@mellanox.com> - 2017-06-08 17:30 +0200 [PATCH 06/11] ARC: [NUMA] added CONFIG_NUMA for plat-eznps Noam Camus <noamca@mellanox.com> - 2017-06-08 17:30 +0200
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