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Groups > linux.kernel > #1660158
| From | Paul Cercueil <paul@crapouillou.net> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH 12/15] MIPS: JZ4770: Work around config2 misreporting associativity |
| Date | 2017-06-07 22:10 +0200 |
| Message-ID | <tPPrb-2PB-3@gated-at.bofh.it> (permalink) |
| References | <tPPrb-2PB-5@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
From: Maarten ter Huurne <maarten@treewalker.org> According to config2, the associativity would be 5-ways, but the documentation states 4-ways, which also matches the documented L2 cache size of 256 kB. Signed-off-by: Maarten ter Huurne <maarten@treewalker.org> --- arch/mips/mm/sc-mips.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c index c909c3342729..67a3b4d88580 100644 --- a/arch/mips/mm/sc-mips.c +++ b/arch/mips/mm/sc-mips.c @@ -15,6 +15,7 @@ #include <asm/mmu_context.h> #include <asm/r4kcache.h> #include <asm/mips-cm.h> +#include <asm/bootinfo.h> /* * MIPS32/MIPS64 L2 cache handling @@ -228,6 +229,14 @@ static inline int __init mips_sc_probe(void) else return 0; + /* + * According to config2 it would be 5-ways, but that is contradicted + * by all documentation. + */ + if (current_cpu_type() == CPU_JZRISC && + mips_machtype == MACH_INGENIC_JZ4770) + c->scache.ways = 4; + c->scache.waysize = c->scache.sets * c->scache.linesz; c->scache.waybit = __ffs(c->scache.waysize); -- 2.11.0
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[PATCH 12/15] MIPS: JZ4770: Work around config2 misreporting associativity Paul Cercueil <paul@crapouillou.net> - 2017-06-07 22:10 +0200
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