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Groups > linux.kernel > #1659904
| From | John Garry <john.garry@huawei.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH v4 22/23] scsi: hisi_sas: add v3 code to fill some more hw function pointers |
| Date | 2017-06-07 17:00 +0200 |
| Message-ID | <tPKBf-7Z0-77@gated-at.bofh.it> (permalink) |
| References | <tPKBc-7Z0-9@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
From: Xiang Chen <chenxiang66@hisilicon.com>
Add code to fill the interface of phy_hard_reset, phy_get_max_linkrate,
and phy enable/disable.
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 39 ++++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index a5816cb..52251ee 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -195,6 +195,8 @@
#define TXID_AUTO (PORT_BASE + 0xb8)
#define CT3_OFF 1
#define CT3_MSK (0x1 << CT3_OFF)
+#define TX_HARDRST_OFF 2
+#define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
#define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
#define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
#define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134)
@@ -664,6 +666,14 @@ static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
}
+static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
+ u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
+
+ cfg &= ~PHY_CFG_ENA_MSK;
+ hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
+}
+
static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
{
config_id_frame_v3_hw(hisi_hba, phy_no);
@@ -671,6 +681,11 @@ static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
enable_phy_v3_hw(hisi_hba, phy_no);
}
+static void stop_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
+ disable_phy_v3_hw(hisi_hba, phy_no);
+}
+
static void start_phys_v3_hw(struct hisi_hba *hisi_hba)
{
int i;
@@ -679,6 +694,26 @@ static void start_phys_v3_hw(struct hisi_hba *hisi_hba)
start_phy_v3_hw(hisi_hba, i);
}
+static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
+ struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
+ u32 txid_auto;
+
+ stop_phy_v3_hw(hisi_hba, phy_no);
+ if (phy->identify.device_type == SAS_END_DEVICE) {
+ txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
+ hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
+ txid_auto | TX_HARDRST_MSK);
+ }
+ msleep(100);
+ start_phy_v3_hw(hisi_hba, phy_no);
+}
+
+enum sas_linkrate phy_get_max_linkrate_v3_hw(void)
+{
+ return SAS_LINK_RATE_12_0_GBPS;
+}
+
static void phys_init_v3_hw(struct hisi_hba *hisi_hba)
{
start_phys_v3_hw(hisi_hba);
@@ -1992,6 +2027,10 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
.start_delivery = start_delivery_v3_hw,
.slot_complete = slot_complete_v3_hw,
.phys_init = phys_init_v3_hw,
+ .phy_enable = enable_phy_v3_hw,
+ .phy_disable = disable_phy_v3_hw,
+ .phy_hard_reset = phy_hard_reset_v3_hw,
+ .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw,
};
static struct Scsi_Host *
--
1.9.1
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[PATCH v4 00/23] hisi_sas: hip08 support John Garry <john.garry@huawei.com> - 2017-06-07 17:00 +0200 [PATCH v4 11/23] scsi: hisi_sas: add v3 hw init John Garry <john.garry@huawei.com> - 2017-06-07 17:00 +0200 [PATCH v4 03/23] scsi: hisi_sas: optimise the usage of hisi_hba.lock John Garry <john.garry@huawei.com> - 2017-06-07 17:00 +0200 [PATCH v4 15/23] scsi: hisi_sas: add v3 code to send SSP frame John Garry <john.garry@huawei.com> - 2017-06-07 17:00 +0200 [PATCH v4 07/23] scsi: hisi_sas: add pci_dev in hisi_hba struct John Garry <john.garry@huawei.com> - 2017-06-07 17:00 +0200 [PATCH v4 20/23] scsi: hisi_sas: add get_wideport_bitmap_v3_hw() John Garry <john.garry@huawei.com> - 2017-06-07 17:00 +0200 [PATCH v4 23/23] scsi: hisi_sas: modify internal abort dev flow for v3 hw John Garry <john.garry@huawei.com> - 2017-06-07 17:00 +0200 [PATCH v4 21/23] scsi: hisi_sas: Add v3 code to support ECC and AXI bus fatal error John Garry <john.garry@huawei.com> - 2017-06-07 17:00 +0200 [PATCH v4 10/23] scsi: hisi_sas: add initialisation for v3 pci-based controller John Garry <john.garry@huawei.com> - 2017-06-07 17:00 +0200 [PATCH v4 19/23] scsi: hisi_sas: add v3 code to send internal abort command John Garry <john.garry@huawei.com> - 2017-06-07 17:00 +0200 [PATCH v4 04/23] scsi: hisi_sas: relocate get_ata_protocol() John Garry <john.garry@huawei.com> - 2017-06-07 17:00 +0200 [PATCH v4 02/23] scsi: hisi_sas: define hisi_sas_device.device_id as int John Garry <john.garry@huawei.com> - 2017-06-07 17:00 +0200 [PATCH v4 12/23] scsi: hisi_sas: add v3 hw PHY init John Garry <john.garry@huawei.com> - 2017-06-07 17:00 +0200 [PATCH v4 17/23] scsi: hisi_sas: add v3 code to send ATA frame John Garry <john.garry@huawei.com> - 2017-06-07 17:00 +0200 [PATCH v4 16/23] scsi: hisi_sas: add v3 code to send SMP frame John Garry <john.garry@huawei.com> - 2017-06-07 17:00 +0200 [PATCH v4 01/23] scsi: hisi_sas: fix timeout check in hisi_sas_internal_task_abort() John Garry <john.garry@huawei.com> - 2017-06-07 17:00 +0200 [PATCH v4 06/23] scsi: hisi_sas: relocate get_ncq_tag_v2_hw() John Garry <john.garry@huawei.com> - 2017-06-07 17:00 +0200 [PATCH v4 13/23] scsi: hisi_sas: add phy up/down/bcast and channel ISR John Garry <john.garry@huawei.com> - 2017-06-07 17:00 +0200 [PATCH v4 18/23] scsi: hisi_sas: add v3 code for itct setup and free John Garry <john.garry@huawei.com> - 2017-06-07 17:00 +0200 [PATCH v4 22/23] scsi: hisi_sas: add v3 code to fill some more hw function pointers John Garry <john.garry@huawei.com> - 2017-06-07 17:00 +0200 [PATCH v4 09/23] scsi: hisi_sas: add skeleton v3 hw driver John Garry <john.garry@huawei.com> - 2017-06-07 17:00 +0200
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