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Groups > linux.kernel > #1659754
| From | Peter Zijlstra <peterz@infradead.org> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH 13/17] RISC-V: Add include subdirectory |
| Date | 2017-06-07 14:40 +0200 |
| Message-ID | <tPIpI-6D4-13@gated-at.bofh.it> (permalink) |
| References | <tK6bn-4ju-3@gated-at.bofh.it> <tPvLP-6UA-3@gated-at.bofh.it> <tPvLR-6UA-49@gated-at.bofh.it> <tPHWG-6rv-19@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On Wed, Jun 07, 2017 at 02:06:13PM +0200, Peter Zijlstra wrote:
> On Tue, Jun 06, 2017 at 04:00:03PM -0700, Palmer Dabbelt wrote:
> What pretty much all the other architectures do is something like:
>
> #define ATOMIC_OP(op, asm_op, c_op) \
> static __always_inline void atomic_##op(int i, atomic_t *v) \
> { \
> __asm__ __volatile__ ( \
> "amo" #asm_op ".w zero, %1, %0" \
> : "+A" (v->counter) \
> : "r" (i)); \
> }
>
> #define ATOMIC_FETCH_OP(op, asm_op, c_op) \
> static __always_inline int atomic_fetch_##op(int i, atomic_t *v)\
> { \
> register int ret; \
> __asm__ __volatile__ ( \
> "amo" #asm_op ".w %2, %1, %0" \
> : "+A" (v->counter), "=r" (ret) \
> : "r" (mask)); \
> return ret; \
> }
>
> #define ATOMIC_OP_RETURN(op, asm_op, c_op) \
> static __always_inline int atomic_##op##_return(int i, atomic_t *v) \
> { \
> return atomic_fetch_##op(i, v) c_op i; \
> }
>
> #define ATOMIC_OPS(op, asm_op, c_op) \
> ATOMIC_OP(op, asm_op, c_op) \
> ATOMIC_OP_RETURN(op, asm_op, c_op) \
> ATOMIC_FETCH_OP(op, asm_op, c_op)
>
> ATOMIC_OPS(add, add, +)
> ATOMIC_OPS(sub, sub, -)
>
> #undef ATOMIC_OPS
>
> #define ATOMIC_OPS(op, asm_op, c_op) \
> ATOMIC_OP(op, asm_op, c_op) \
> ATOMIC_FETCH_OP(op, asm_op, c_op)
>
> ATOMIC_OPS(and, and, &)
> ATOMIC_OPS(or, or, |)
> ATOMIC_OPS(xor, xor, ^)
>
> #undef ATOMIC_OPS
>
> Which is much simpler no?
In fact, after having read your manual you'd want something like:
#define ATOMIC_OP(op, asm_op, c_op) \
static __always_inline void atomic_##op(int i, atomic_t *v) \
{ \
__asm__ __volatile__ ( \
"amo" #asm_op ".w zero, %1, %0" \
: "+A" (v->counter) \
: "r" (i)); \
}
#define ATOMIC_FETCH_OP(op, asm_op, c_op, asm_or, order) \
static __always_inline int atomic_fetch_##op##order(int i, atomic_t *v)\
{ \
register int ret; \
__asm__ __volatile__ ( \
"amo" #asm_op ".w" #asm_or " %2, %1, %0" \
: "+A" (v->counter), "=r" (ret) \
: "r" (mask)); \
return ret; \
}
#define ATOMIC_OP_RETURN(op, asm_op, c_op, asm_or, order) \
static __always_inline int atomic_##op##_return##order(int i, atomic_t *v) \
{ \
return atomic_fetch_##op##order(i, v) c_op i; \
}
#define ATOMIC_OPS(op, asm_op, c_op) \
ATOMIC_OP(op, asm_op, c_op, , _relaxed) \
ATOMIC_OP_RETURN(op, asm_op, c_op, , _relaxed) \
ATOMIC_FETCH_OP(op, asm_op, c_op, , _relaxed)
ATOMIC_OPS(add, add, +)
ATOMIC_OPS(sub, sub, -)
#undef ATOMIC_OPS
#define ATOMIC_OPS(op, asm_op, c_op, asm_or, order) \
ATOMIC_OP_RETURN(op, asm_op, c_op, , _relaxed) \
ATOMIC_FETCH_OP(op, asm_op, c_op, , _relaxed)
ATOMIC_OPS(add, add, +, ".aq", _acquire)
ATOMIC_OPS(add, add, +, ".rl", _release)
ATOMIC_OPS(add, add, +, ".aq.rl", )
ATOMIC_OPS(sub, sub, -, ".aq", _acquire)
ATOMIC_OPS(sub, sub, -, ".rl", _release)
ATOMIC_OPS(sub, sub, -, ".aq.rl", )
#undef ATOMIC_OPS
#define ATOMIC_OPS(op, asm_op, c_op) \
ATOMIC_OP(op, asm_op, c_op) \
ATOMIC_FETCH_OP(op, asm_op, c_op, , _relaxed)
ATOMIC_OPS(and, and, &)
ATOMIC_OPS(or, or, |)
ATOMIC_OPS(xor, xor, ^)
#undef ATOMIC_OPS
ATOMIC_FETCH_OP(and, and, &, ".aq", _acquire)
ATOMIC_FETCH_OP(and, and, &, ".rl", _release)
ATOMIC_FETCH_OP(and, and, &, ".aq.rl", )
ATOMIC_FETCH_OP(or, or, |, ".aq", _acquire)
ATOMIC_FETCH_OP(or, or, |, ".rl", _release)
ATOMIC_FETCH_OP(or, or, |, ".aq.rl", )
ATOMIC_FETCH_OP(xor, xor, ^, ".aq", _acquire)
ATOMIC_FETCH_OP(xor, xor, ^, ".rl", _release)
ATOMIC_FETCH_OP(xor, xor, ^, ".aq.rl", )
#define smp_mb__before_atomic() smp_mb()
#define smp_mb__after_atomic() smp_mb()
Which (pending the sub confusion) will generate the entire set of:
atomic_add, atomic_add_return{_relaxed,_acquire,_release,} atomic_fetch_add{_relaxed,_acquire,_release,}
atomic_sub, atomic_sub_return{_relaxed,_acquire,_release,} atomic_fetch_sub{_relaxed,_acquire,_release,}
atomic_and, atomic_fetch_and{_relaxed,_acquire,_release,}
atomic_or, atomic_fetch_or{_relaxed,_acquire,_release,}
atomic_xor, atomic_fetch_xor{_relaxed,_acquire,_release,}
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RISC-V Linux Port v2 Palmer Dabbelt <palmer@dabbelt.com> - 2017-06-07 01:10 +0200
[PATCH 06/17] pci: Add generic pcibios_{fixup_bus,align_resource} Palmer Dabbelt <palmer@dabbelt.com> - 2017-06-07 01:10 +0200
Re: [PATCH 06/17] pci: Add generic pcibios_{fixup_bus,align_resource} Geert Uytterhoeven <geert@linux-m68k.org> - 2017-06-07 09:30 +0200
Re: [PATCH 06/17] pci: Add generic pcibios_{fixup_bus,align_resource} Arnd Bergmann <arnd@arndb.de> - 2017-06-07 10:10 +0200
Re: [PATCH 06/17] pci: Add generic pcibios_{fixup_bus,align_resource} Christoph Hellwig <hch@infradead.org> - 2017-06-08 10:20 +0200
Re: [PATCH 06/17] pci: Add generic pcibios_{fixup_bus,align_resource} Arnd Bergmann <arnd@arndb.de> - 2017-06-08 10:40 +0200
[PATCH 08/17] dts: include documentation for the RISC-V interrupt controllers Palmer Dabbelt <palmer@dabbelt.com> - 2017-06-07 01:10 +0200
Re: [PATCH 08/17] dts: include documentation for the RISC-V interrupt controllers Geert Uytterhoeven <geert@linux-m68k.org> - 2017-06-07 09:20 +0200
Re: [PATCH 08/17] dts: include documentation for the RISC-V interrupt controllers Mark Rutland <mark.rutland@arm.com> - 2017-06-07 12:20 +0200
Re: [PATCH 08/17] dts: include documentation for the RISC-V interrupt controllers Wesley Terpstra <wesley@sifive.com> - 2017-06-07 21:00 +0200
Re: [PATCH 08/17] dts: include documentation for the RISC-V interrupt controllers Rob Herring <robh+dt@kernel.org> - 2017-06-07 22:00 +0200
Re: [PATCH 08/17] dts: include documentation for the RISC-V interrupt controllers Wesley Terpstra <wesley@sifive.com> - 2017-06-07 22:40 +0200
Re: [PATCH 08/17] dts: include documentation for the RISC-V interrupt controllers Mark Rutland <mark.rutland@arm.com> - 2017-06-08 13:00 +0200
Re: [PATCH 08/17] dts: include documentation for the RISC-V interrupt controllers Wesley Terpstra <wesley@sifive.com> - 2017-06-09 23:50 +0200
Re: [PATCH 08/17] dts: include documentation for the RISC-V interrupt controllers Wesley Terpstra <wesley@sifive.com> - 2017-06-10 00:00 +0200
Re: [PATCH 08/17] dts: include documentation for the RISC-V interrupt controllers Mark Rutland <mark.rutland@arm.com> - 2017-06-19 16:40 +0200
Re: [PATCH 08/17] dts: include documentation for the RISC-V interrupt controllers "Luis R. Rodriguez" <mcgrof@kernel.org> - 2017-06-08 00:30 +0200
[PATCH 11/17] irqchip: RISC-V Local Interrupt Controller Driver Palmer Dabbelt <palmer@dabbelt.com> - 2017-06-07 01:10 +0200
Re: [PATCH 11/17] irqchip: RISC-V Local Interrupt Controller Driver Geert Uytterhoeven <geert@linux-m68k.org> - 2017-06-07 09:20 +0200
[PATCH 01/17] drivers: support PCIe in RISCV Palmer Dabbelt <palmer@dabbelt.com> - 2017-06-07 01:10 +0200
Re: [PATCH 01/17] drivers: support PCIe in RISCV Geert Uytterhoeven <geert@linux-m68k.org> - 2017-06-07 09:20 +0200
Re: [PATCH 01/17] drivers: support PCIe in RISCV Christoph Hellwig <hch@infradead.org> - 2017-06-07 16:30 +0200
Re: [PATCH 01/17] drivers: support PCIe in RISCV Olof Johansson <olof@lixom.net> - 2017-06-07 19:50 +0200
[PATCH 15/17] RISC-V: Add mm subdirectory Palmer Dabbelt <palmer@dabbelt.com> - 2017-06-07 01:10 +0200
[PATCH 09/17] clocksource/timer-riscv: New RISC-V Clocksource Palmer Dabbelt <palmer@dabbelt.com> - 2017-06-07 01:10 +0200
Re: [PATCH 09/17] clocksource/timer-riscv: New RISC-V Clocksource Geert Uytterhoeven <geert@linux-m68k.org> - 2017-06-07 09:20 +0200
Re: [PATCH 09/17] clocksource/timer-riscv: New RISC-V Clocksource Arnd Bergmann <arnd@arndb.de> - 2017-06-07 09:30 +0200
Re: [PATCH 09/17] clocksource/timer-riscv: New RISC-V Clocksource Marc Zyngier <marc.zyngier@arm.com> - 2017-06-07 11:50 +0200
Re: RISC-V Linux Port v2 David Howells <dhowells@redhat.com> - 2017-06-07 09:30 +0200
Re: RISC-V Linux Port v2 Palmer Dabbelt <palmer@dabbelt.com> - 2017-06-08 00:00 +0200
Re: [PATCH 13/17] RISC-V: Add include subdirectory Arnd Bergmann <arnd@arndb.de> - 2017-06-07 10:20 +0200
Re: RISC-V Linux Port v2 Will Deacon <will.deacon@arm.com> - 2017-06-07 11:30 +0200
Re: RISC-V Linux Port v2 Palmer Dabbelt <palmer@dabbelt.com> - 2017-06-08 00:00 +0200
Re: RISC-V Linux Port v2 Will Deacon <will.deacon@arm.com> - 2017-06-08 12:30 +0200
Re: RISC-V Linux Port v2 Palmer Dabbelt <palmer@dabbelt.com> - 2017-06-08 20:20 +0200
Re: [PATCH 13/17] RISC-V: Add include subdirectory Peter Zijlstra <peterz@infradead.org> - 2017-06-07 14:00 +0200
Re: [PATCH 13/17] RISC-V: Add include subdirectory Peter Zijlstra <peterz@infradead.org> - 2017-06-07 14:30 +0200
Re: [PATCH 13/17] RISC-V: Add include subdirectory Peter Zijlstra <peterz@infradead.org> - 2017-06-07 14:10 +0200
Re: [PATCH 13/17] RISC-V: Add include subdirectory Peter Zijlstra <peterz@infradead.org> - 2017-06-07 14:30 +0200
Re: [PATCH 13/17] RISC-V: Add include subdirectory Peter Zijlstra <peterz@infradead.org> - 2017-06-07 14:40 +0200
Re: [PATCH 13/17] RISC-V: Add include subdirectory Peter Zijlstra <peterz@infradead.org> - 2017-06-07 15:00 +0200
Re: [PATCH 13/17] RISC-V: Add include subdirectory Will Deacon <will.deacon@arm.com> - 2017-06-07 15:20 +0200
Re: [PATCH 13/17] RISC-V: Add include subdirectory Peter Zijlstra <peterz@infradead.org> - 2017-06-07 18:40 +0200
Re: [PATCH 13/17] RISC-V: Add include subdirectory Peter Zijlstra <peterz@infradead.org> - 2017-06-07 14:50 +0200
Re: [PATCH 13/17] RISC-V: Add include subdirectory Peter Zijlstra <peterz@infradead.org> - 2017-06-07 15:20 +0200
Re: [PATCH 13/17] RISC-V: Add include subdirectory Peter Zijlstra <peterz@infradead.org> - 2017-06-09 10:20 +0200
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