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Groups > linux.kernel > #1656594
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| From | Jacek Anaszewski <jacek.anaszewski@gmail.com> |
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH 7/9] [media] s5p-jpeg: Change sclk_jpeg to 166MHz for Exynos5250 |
| Date | Sat, 03 Jun 2017 00:00:02 +0200 |
| Message-ID | <tO2LU-6Ey-29@gated-at.bofh.it> (permalink) |
| References | <tNXjb-3qc-3@gated-at.bofh.it> <tNXjc-3qc-27@gated-at.bofh.it> |
| X-Original-To | Thierry Escande <thierry.escande@collabora.com>, Andrzej Pietrasiewicz <andrzej.p@samsung.com>, Mauro Carvalho Chehab <mchehab@kernel.org> |
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| X-Original-Cc | linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, Marek Szyprowski <m.szyprowski@samsung.com>, Sylwester Nawrocki <s.nawrocki@samsung.com> |
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Cc Marek and Sylwester.
On 06/02/2017 06:02 PM, Thierry Escande wrote:
> From: henryhsu <henryhsu@chromium.org>
>
> The default clock parent of jpeg on Exynos5250 is fin_pll, which is
> 24MHz. We have to change the clock parent to CPLL, which is 333MHz,
> and set sclk_jpeg to 166MHz.
>
> Signed-off-by: Heng-Ruey Hsu <henryhsu@chromium.org>
> Signed-off-by: Thierry Escande <thierry.escande@collabora.com>
> ---
> drivers/media/platform/s5p-jpeg/jpeg-core.c | 47 +++++++++++++++++++++++++++++
> 1 file changed, 47 insertions(+)
>
> diff --git a/drivers/media/platform/s5p-jpeg/jpeg-core.c b/drivers/media/platform/s5p-jpeg/jpeg-core.c
> index 7a7acbc..430e925 100644
> --- a/drivers/media/platform/s5p-jpeg/jpeg-core.c
> +++ b/drivers/media/platform/s5p-jpeg/jpeg-core.c
> @@ -969,6 +969,44 @@ static void exynos4_jpeg_parse_q_tbl(struct s5p_jpeg_ctx *ctx)
> }
> }
>
> +static int exynos4_jpeg_set_sclk_rate(struct s5p_jpeg *jpeg, struct clk *sclk)
Why here exynos4 and in the subject Exynos5250?
> +{
> + struct clk *mout_jpeg;
> + struct clk *sclk_cpll;
> + int ret;
> +
> + mout_jpeg = clk_get(jpeg->dev, "mout_jpeg");
> + if (IS_ERR(mout_jpeg)) {
> + dev_err(jpeg->dev, "mout_jpeg clock not available: %ld\n",
> + PTR_ERR(mout_jpeg));
> + return PTR_ERR(mout_jpeg);
> + }
> +
> + sclk_cpll = clk_get(jpeg->dev, "sclk_cpll");
> + if (IS_ERR(sclk_cpll)) {
> + dev_err(jpeg->dev, "sclk_cpll clock not available: %ld\n",
> + PTR_ERR(sclk_cpll));
> + clk_put(mout_jpeg);
> + return PTR_ERR(sclk_cpll);
> + }
> +
> + ret = clk_set_parent(mout_jpeg, sclk_cpll);
> + clk_put(sclk_cpll);
> + clk_put(mout_jpeg);
> + if (ret) {
> + dev_err(jpeg->dev, "clk_set_parent failed: %d\n", ret);
> + return ret;
> + }
> +
> + ret = clk_set_rate(sclk, 166500 * 1000);
> + if (ret) {
> + dev_err(jpeg->dev, "clk_set_rate failed: %d\n", ret);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> #if defined(CONFIG_EXYNOS_IOMMU) && defined(CONFIG_ARM_DMA_USE_IOMMU)
> static int jpeg_iommu_init(struct platform_device *pdev)
> {
> @@ -2974,6 +3012,15 @@ static int s5p_jpeg_probe(struct platform_device *pdev)
> jpeg->variant->clk_names[i]);
> return PTR_ERR(jpeg->clocks[i]);
> }
> +
> + if (jpeg->variant->version == SJPEG_EXYNOS4 &&
> + !strncmp(jpeg->variant->clk_names[i],
> + "sclk", strlen("sclk"))) {
> + ret = exynos4_jpeg_set_sclk_rate(jpeg,
> + jpeg->clocks[i]);
> + if (ret)
> + return ret;
> + }
> }
>
> /* v4l2 device */
>
--
Best regards,
Jacek Anaszewski
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[PATCH 0/9] [media] s5p-jpeg: Various fixes and improvements Thierry Escande <thierry.escande@collabora.com> - 2017-06-02 18:10 +0200
[PATCH 5/9] [media] s5p-jpeg: Add IOMMU support Thierry Escande <thierry.escande@collabora.com> - 2017-06-02 18:10 +0200
Re: [PATCH 5/9] [media] s5p-jpeg: Add IOMMU support Jacek Anaszewski <jacek.anaszewski@gmail.com> - 2017-06-02 23:50 +0200
Re: [PATCH 5/9] [media] s5p-jpeg: Add IOMMU support Shuah Khan <shuahkhan@gmail.com> - 2017-06-03 02:50 +0200
Re: [PATCH 5/9] [media] s5p-jpeg: Add IOMMU support Sylwester Nawrocki <s.nawrocki@samsung.com> - 2017-06-05 13:40 +0200
[PATCH 2/9] [media] s5p-jpeg: Call jpeg_bound_align_image after qbuf Thierry Escande <thierry.escande@collabora.com> - 2017-06-02 18:10 +0200
Re: [PATCH 2/9] [media] s5p-jpeg: Call jpeg_bound_align_image after qbuf Jacek Anaszewski <jacek.anaszewski@gmail.com> - 2017-06-02 23:30 +0200
[PATCH 7/9] [media] s5p-jpeg: Change sclk_jpeg to 166MHz for Exynos5250 Thierry Escande <thierry.escande@collabora.com> - 2017-06-02 18:10 +0200
Re: [PATCH 7/9] [media] s5p-jpeg: Change sclk_jpeg to 166MHz for Exynos5250 Jacek Anaszewski <jacek.anaszewski@gmail.com> - 2017-06-03 00:00 +0200
Re: [PATCH 7/9] [media] s5p-jpeg: Change sclk_jpeg to 166MHz for Exynos5250 Sylwester Nawrocki <s.nawrocki@samsung.com> - 2017-06-05 12:30 +0200
[PATCH 1/9] [media] s5p-jpeg: Reset the Codec before doing a soft reset Thierry Escande <thierry.escande@collabora.com> - 2017-06-02 18:10 +0200
Re: [PATCH 1/9] [media] s5p-jpeg: Reset the Codec before doing a soft reset Jacek Anaszewski <jacek.anaszewski@gmail.com> - 2017-06-02 22:00 +0200
Re: [PATCH 1/9] [media] s5p-jpeg: Reset the Codec before doing a soft reset Thierry Escande <thierry.escande@collabora.com> - 2017-06-07 14:40 +0200
[PATCH 4/9] [media] s5p-jpeg: Decode 4:1:1 chroma subsampling format Thierry Escande <thierry.escande@collabora.com> - 2017-06-02 18:10 +0200
Re: [PATCH 4/9] [media] s5p-jpeg: Decode 4:1:1 chroma subsampling format Jacek Anaszewski <jacek.anaszewski@gmail.com> - 2017-06-02 23:40 +0200
[PATCH 3/9] [media] s5p-jpeg: Correct WARN_ON statement for checking subsampling Thierry Escande <thierry.escande@collabora.com> - 2017-06-02 18:10 +0200
[PATCH 9/9] [media] s5p-jpeg: Add support for multi-planar APIs Thierry Escande <thierry.escande@collabora.com> - 2017-06-02 18:10 +0200
Re: [PATCH 9/9] [media] s5p-jpeg: Add support for multi-planar APIs Jacek Anaszewski <jacek.anaszewski@gmail.com> - 2017-06-03 00:10 +0200
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