Re: [PATCHv1, RFC 0/8] Boot-time switching between 4- and 5-level paging

From	"Kirill A. Shutemov" <kirill@shutemov.name>
Newsgroups	linux.kernel
Subject	Re: [PATCHv1, RFC 0/8] Boot-time switching between 4- and 5-level paging
Date	2017-05-26 18:00 +0200
Message-ID	<tLpOG-7Ks-21@gated-at.bofh.it> (permalink)
References	<tL7I5-4wz-3@gated-at.bofh.it> <tLamB-6m2-1@gated-at.bofh.it> <tLna9-6jc-11@gated-at.bofh.it> <tLpOG-7Ks-17@gated-at.bofh.it>
Organization	linux.* mail to news gateway

Show all headers | View raw

On Fri, May 26, 2017 at 08:51:48AM -0700, Linus Torvalds wrote:
> On Fri, May 26, 2017 at 6:00 AM, Kirill A. Shutemov
> <kirill@shutemov.name> wrote:
> >
> > I don't see how kernel threads can use 4-level paging. It doesn't work
> > from virtual memory layout POV. Kernel claims half of full virtual address
> > space for itself -- 256 PGD entries, not one as we would effectively have
> > in case of switching to 4-level paging. For instance, addresses, where
> > vmalloc and vmemmap are mapped, are not canonical with 4-level paging.
> 
> I would have just assumed we'd map the kernel in the shared part that
> fits in the top 47 bits.
> 
> But it sounds like you can't switch back and forth anyway, so I guess it's moot.
> 
> Where *is* the LA57 documentation, btw? I had an old x86 architecture
> manual, so I updated it, but LA57 isn't mentioned in the new one
> either.

It's in a separate white paper for now:

https://software.intel.com/sites/default/files/managed/2b/80/5-level_paging_white_paper.pdf

-- 
 Kirill A. Shutemov

Thread

[PATCHv1, RFC 0/8] Boot-time switching between 4- and 5-level paging "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> - 2017-05-25 22:40 +0200
  [PATCHv1, RFC 2/8] x86/mm: Make virtual memory layout movable for CONFIG_X86_5LEVEL "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> - 2017-05-25 22:40 +0200
  Re: [PATCHv1, RFC 0/8] Boot-time switching between 4- and 5-level paging Linus Torvalds <torvalds@linux-foundation.org> - 2017-05-26 01:30 +0200
    Re: [PATCHv1, RFC 0/8] Boot-time switching between 4- and 5-level paging Andy Lutomirski <luto@kernel.org> - 2017-05-26 02:50 +0200
      Re: [PATCHv1, RFC 0/8] Boot-time switching between 4- and 5-level  paging Kevin Easton <kevin@guarana.org> - 2017-05-26 06:30 +0200
        Re: [PATCHv1, RFC 0/8] Boot-time switching between 4- and 5-level paging Andy Lutomirski <luto@kernel.org> - 2017-05-26 09:30 +0200
    Re: [PATCHv1, RFC 0/8] Boot-time switching between 4- and 5-level  paging "Kirill A. Shutemov" <kirill@shutemov.name> - 2017-05-26 15:10 +0200
      Re: [PATCHv1, RFC 0/8] Boot-time switching between 4- and 5-level  paging Andi Kleen <ak@linux.intel.com> - 2017-05-26 15:40 +0200
      Re: [PATCHv1, RFC 0/8] Boot-time switching between 4- and 5-level paging Linus Torvalds <torvalds@linux-foundation.org> - 2017-05-26 18:00 +0200
        Re: [PATCHv1, RFC 0/8] Boot-time switching between 4- and 5-level  paging "Kirill A. Shutemov" <kirill@shutemov.name> - 2017-05-26 18:00 +0200
          Re: [PATCHv1, RFC 0/8] Boot-time switching between 4- and 5-level paging Linus Torvalds <torvalds@linux-foundation.org> - 2017-05-26 18:20 +0200
        Re: [PATCHv1, RFC 0/8] Boot-time switching between 4- and 5-level  paging Dave Hansen <dave.hansen@intel.com> - 2017-05-26 21:30 +0200
          Re: [PATCHv1, RFC 0/8] Boot-time switching between 4- and 5-level paging hpa@zytor.com - 2017-05-26 21:50 +0200
        Re: [PATCHv1, RFC 0/8] Boot-time switching between 4- and 5-level paging hpa@zytor.com - 2017-05-26 21:30 +0200
      Re: [PATCHv1, RFC 0/8] Boot-time switching between 4- and 5-level paging hpa@zytor.com - 2017-05-26 22:20 +0200

csiph-web