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Re: [Q] What about PCI mmio access alignment?

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On Thu, May 25, 2017 at 1:12 PM, Du, Changbin <changbin.du@intel.com> wrote:
> I have a basic quesion about the alignment when access PCI bar mmio space. Is
> the address accessed must be DW aligned and count must be DW aligned?

I guess the best answer is PCI architecture specification.
Book I have nearby tells me IIDnMS that yes, you have to follow alignment.

> As far as I know, The address field of TLB ignore lower 2 bits and the unit of
> length field also is DW. So does it mean above question is Yes? Else will CPU
> handle unaligned access for mmio space?

Here you perhaps meant the bus, not the CPU. PCI allows it as long as
actual device allows it.

(I recall patch series that tries to micro optimize PCI config space
access by grouping some bytes into words or even dwords, and it was
rejected).

> I want to know wether below access illegal or not:
>   - readb(bar0)
>   - readb(bar0 + 1)
>   - readl(bar0)

It depends.

-- 
With Best Regards,
Andy Shevchenko

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[Q] What about PCI mmio access alignment? "Du, Changbin" <changbin.du@intel.com> - 2017-05-25 12:20 +0200
  Re: [Q] What about PCI mmio access alignment? Andy Shevchenko <andy.shevchenko@gmail.com> - 2017-05-27 17:40 +0200
    Re: [Q] What about PCI mmio access alignment? "Du, Changbin" <changbin.du@intel.com> - 2017-05-28 13:00 +0200

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