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Re: [PATCH 5/7] clk: mvebu: cp110: add sdio clock to cp-110 system controller

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On Fri, May 19, 2017 at 05:55:23PM +0200, Gregory CLEMENT wrote:
> From: Konstantin Porotchkin <kostap@marvell.com>
> 
> This commit updates the CP110 system controller driver to add the
> definition for a missing clock.
> 
> The SDIO clock is dedicated driving the SDHCI interface and its frequency
> is 400MHz (2/5 of PLL source clock).
> 
> The SDIO interface should be bound to this clock and not the core clock
> as in the older code.
> Using the wrong clock lead to a maximum SDHCI frequency of 250 Mhz, while
> the HW really supports up to 400 Mhz.
> 
> This patch also fixes the NAND clock relationship documentation.
> 
> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
> [gregory.clement@free-electrons.com:
> - use sdio instead of emmc to name the clock
> - update binding documentation]
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
>  Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt |  1 +
>  drivers/clk/mvebu/cp110-system-controller.c                                | 28 +++++++++++++++++++++++-----
>  2 files changed, 24 insertions(+), 5 deletions(-)

Acked-by: Rob Herring <robh@kernel.org>

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[PATCH 0/7] Improve cp110 clk support on Marvell Armada 7K/8K Gregory CLEMENT <gregory.clement@free-electrons.com> - 2017-05-19 18:00 +0200
  [PATCH 5/7] clk: mvebu: cp110: add sdio clock to cp-110 system controller Gregory CLEMENT <gregory.clement@free-electrons.com> - 2017-05-19 18:00 +0200
    Re: [PATCH 5/7] clk: mvebu: cp110: add sdio clock to cp-110 system  controller Rob Herring <robh@kernel.org> - 2017-05-23 17:30 +0200

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