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Re: [PATCH v2] drm/pl111: Register the clock divider and use it.

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Linus Walleij <linus.walleij@linaro.org> writes:

> On Mon, May 8, 2017 at 9:33 PM, Eric Anholt <eric@anholt.net> wrote:
>
>> This is required for the panel to work on bcm911360, where CLCDCLK is
>> the fixed 200Mhz AXI41 clock.  The rate set is still passed up to the
>> CLCDCLK, for platforms that have a settable rate on that one.
>>
>> v2: Set SET_RATE_PARENT (caught by Linus Walleij), depend on
>>     COMMON_CLK.
>>
>> Signed-off-by: Eric Anholt <eric@anholt.net>
>
> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>

Thanks.  Waiting on an ack from clock folks, then we'll be ready to go,
I think.

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Thread

[PATCH v2] drm/pl111: Register the clock divider and use it. Eric Anholt <eric@anholt.net> - 2017-05-08 21:40 +0200
  Re: [PATCH v2] drm/pl111: Register the clock divider and use it. Linus Walleij <linus.walleij@linaro.org> - 2017-05-08 23:50 +0200
    Re: [PATCH v2] drm/pl111: Register the clock divider and use it. Eric Anholt <eric@anholt.net> - 2017-05-09 20:20 +0200
      Re: [PATCH v2] drm/pl111: Register the clock divider and use it. Linus Walleij <linus.walleij@linaro.org> - 2017-05-10 14:40 +0200

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