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Re: [PATCH] net: ethernet: ti: cpsw: adjust cpsw fifos depth for fullduplex flow control

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From: Grygorii Strashko <grygorii.strashko@ti.com>
Date: Mon, 8 May 2017 14:21:21 -0500

> When users set flow control using ethtool the bits are set properly in the
> CPGMAC_SL MACCONTROL register, but the FIFO depth in the respective Port n
> Maximum FIFO Blocks (Pn_MAX_BLKS) registers remains set to the minimum size
> reset value. When receive flow control is enabled on a port, the port's
> associated FIFO block allocation must be adjusted. The port RX allocation
> must increase to accommodate the flow control runout. The TRM recommends
> numbers of 5 or 6.
> 
> Hence, apply required Port FIFO configuration to
> Pn_MAX_BLKS.Pn_TX_MAX_BLKS=0xF and Pn_MAX_BLKS.Pn_RX_MAX_BLKS=0x5 during
> interface initialization.
> 
> Cc: Schuyler Patton <spatton@ti.com>
> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>

Applied.

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[PATCH] net: ethernet: ti: cpsw: adjust cpsw fifos depth for fullduplex flow control Grygorii Strashko <grygorii.strashko@ti.com> - 2017-05-08 21:30 +0200
  Re: [PATCH] net: ethernet: ti: cpsw: adjust cpsw fifos depth for  fullduplex flow control David Miller <davem@davemloft.net> - 2017-05-08 23:40 +0200

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