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Groups > linux.kernel > #1635479
| From | Arnd Bergmann <arnd@arndb.de> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH 1/4] mmc: sdhci-esdhc: Add SDHCI_QUIRK_32BIT_DMA_ADDR |
| Date | 2017-05-04 10:50 +0200 |
| Message-ID | <tDkCt-12n-1@gated-at.bofh.it> (permalink) |
| References | <tCZy1-3Rz-3@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On Wed, May 3, 2017 at 12:05 PM, Benoît Thébaudeau <benoit@wsystem.com> wrote:
> The eSDHC can only DMA from 32-bit-aligned addresses.
>
> This fixes the following test cases of mmc_test:
> 11: Badly aligned write
> 12: Badly aligned read
> 13: Badly aligned multi-block write
> 14: Badly aligned multi-block read
>
> Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com>
Is this the right description? I thought that SDHCI_QUIRK_32BIT_DMA_ADDR
was for devices that cannot address high memory above 0xffffffff, rather than
requiring a specific alignment.
If this is indeed an address range problem rather than an alignment problem,
are you sure it is the SD controller that is wrong here, rather than having a
64-bit DMA capable SDHCI connected to a 32-bit parent bus? In the
latter case, the dma-ranges property in the parent bus should limit
the addressing, not the device.
Arnd
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[PATCH 1/4] mmc: sdhci-esdhc: Add SDHCI_QUIRK_32BIT_DMA_ADDR Benoît Thébaudeau <benoit@wsystem.com> - 2017-05-03 12:20 +0200
[PATCH 4/4] mmc: sdhci-esdhc-imx: Remove the ENGcm07207 workaround Benoît Thébaudeau <benoit@wsystem.com> - 2017-05-03 12:20 +0200
[PATCH 3/4] mmc: sdhci-esdhc-imx: Allow all supported prescaler values Benoît Thébaudeau <benoit@wsystem.com> - 2017-05-03 12:20 +0200
Re: [PATCH 1/4] mmc: sdhci-esdhc: Add SDHCI_QUIRK_32BIT_DMA_ADDR Arnd Bergmann <arnd@arndb.de> - 2017-05-04 10:50 +0200
Re: [PATCH 1/4] mmc: sdhci-esdhc: Add SDHCI_QUIRK_32BIT_DMA_ADDR Benoît Thébaudeau <benoit@wsystem.com> - 2017-05-04 11:10 +0200
Re: [PATCH 1/4] mmc: sdhci-esdhc: Add SDHCI_QUIRK_32BIT_DMA_ADDR Arnd Bergmann <arnd@arndb.de> - 2017-05-04 11:40 +0200
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