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Re: [PATCH v2 3/8] clk: sunxi-ng: Add class of phase clocks supporting MMC new timing modes

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Hi,

On Wed, May 03, 2017 at 11:16:53AM +0800, Chen-Yu Tsai wrote:
> The MMC clocks on newer SoCs, such as the A83T and H3, support the
> "new timing mode". Under this mode, the output of the clock is divided
> by 2, and the clock delays no longer apply.
> 
> Due to how the clock tree is modeled and setup, we need to model
> this function in two places, the master mmc clock and the two
> child phase clocks. In the mmc clock, we can easily model the
> mode bit as an extra variable post-divider. In the phase clocks,
> we check the bit and return -ENOTSUPP if the bit is set, signaling
> that the phase clocks are not to be used.
> 
> This patch introduces a class of phase clocks that checks the
> timing mode bit.

We've been over this quite some times already...

How do you retrieve the mode used in the clock so that you can also
switch the MMC driver in the new mode?

And do you prevent that from happening on the DT we already have that
use the old clock drivers that do not support this new timing at all?

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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[PATCH v2 3/8] clk: sunxi-ng: Add class of phase clocks supporting MMC new timing modes Chen-Yu Tsai <wens@csie.org> - 2017-05-03 05:20 +0200
  Re: [PATCH v2 3/8] clk: sunxi-ng: Add class of phase clocks  supporting MMC new timing modes Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-05-03 22:40 +0200
    Re: [PATCH v2 3/8] clk: sunxi-ng: Add class of phase clocks  supporting MMC new timing modes Chen-Yu Tsai <wens@csie.org> - 2017-05-04 05:10 +0200
      Re: [PATCH v2 3/8] clk: sunxi-ng: Add class of phase clocks  supporting MMC new timing modes Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-05-05 10:00 +0200

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