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Re: [PATCH 3/4] x86/PCI: Enable a 64bit BAR on AMD Family 15h (Models 30h-3fh) Processors v2

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On Tue, Apr 25, 2017 at 4:19 PM, Christian König
<deathsimple@vodafone.de> wrote:
> From: Christian König <christian.koenig@amd.com>
>
> Most BIOS don't enable this because of compatibility reasons.
>
> Manually enable a 64bit BAR of 64GB size so that we have
> enough room for PCI devices.

> +static void pci_amd_enable_64bit_bar(struct pci_dev *dev)
> +{

> +       uint32_t base, limit, high;

Is u32 or uint32_t used actually in this file?

> +       struct resource *res, *conflict;

> +       unsigned i;

unsigned int i;

Reversed tree order.

> +       for (i = 0; i < 8; ++i) {
> +               pci_read_config_dword(dev, 0x80 + i * 0x8, &base);
> +               pci_read_config_dword(dev, 0x180 + i * 0x4, &high);
> +
> +               /* Is this slot free? */
> +               if ((base & 0x3) == 0x0)
> +                       break;
> +
> +               base >>= 8;
> +               base |= high << 24;
> +
> +               /* Abort if a slot already configures a 64bit BAR. */
> +               if (base > 0x10000)
> +                       return;
> +       }
> +       if (i == 8)
> +               return;
> +
> +       res = kzalloc(sizeof(*res), GFP_KERNEL);
> +       if (!res)
> +               return;
> +
> +       res->name = "PCI Bus 0000:00";

> +       res->flags = IORESOURCE_PREFETCH | IORESOURCE_MEM |
> +               IORESOURCE_MEM_64 | IORESOURCE_WINDOW;

You are using this constant twice AFAICS, perhaps define it in generic
pci.h and re-use?

> +       res->start = 0x100000000;
> +       res->end = 0xfd00000000 - 1;

Perhaps you forgot ul / ull in many places in your code. Care to
compile for 32-bit and fix the warnings?

> +       dev_info(&dev->dev, "adding root bus resource %pR\n", res);

Some of your messages I think are rather dev_dbg() than dev_info().

> +       base = ((res->start >> 8) & 0xffffff00) | 0x3;
> +       limit = ((res->end + 1) >> 8) & 0xffffff00;
> +       high = ((res->start >> 40) & 0xff) |
> +               ((((res->end + 1) >> 40) & 0xff) << 16);

It would be nice to have the magics defined (just on top of this function) like

#define PCI_AMD_BAR_XXX_MASK GENMASK(...)
#define PCI_AMD_BAR_XXX_SHIFT nn

> +       pci_write_config_dword(dev, 0x180 + i * 0x4, high);
> +       pci_write_config_dword(dev, 0x84 + i * 0x8, limit);
> +       pci_write_config_dword(dev, 0x80 + i * 0x8, base);

Ditto for pos:s.

> +
> +       pci_bus_add_resource(dev->bus, res, 0);
> +}

-- 
With Best Regards,
Andy Shevchenko

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Thread

Resizeable PCI BAR support V4 Christian König <deathsimple@vodafone.de> - 2017-04-25 15:30 +0200
  [PATCH 1/4] PCI: add resizeable BAR infrastructure v4 Christian König <deathsimple@vodafone.de> - 2017-04-25 15:30 +0200
    Re: [PATCH 1/4] PCI: add resizeable BAR infrastructure v4 Alex Deucher <alexdeucher@gmail.com> - 2017-04-25 17:10 +0200
    Re: [PATCH 1/4] PCI: add resizeable BAR infrastructure v4 Andy Shevchenko <andy.shevchenko@gmail.com> - 2017-04-26 18:50 +0200
      Re: [PATCH 1/4] PCI: add resizeable BAR infrastructure v4 Christian König <deathsimple@vodafone.de> - 2017-05-02 17:00 +0200
  [PATCH 2/4] PCI: add functionality for resizing resources v3 Christian König <deathsimple@vodafone.de> - 2017-04-25 15:30 +0200
    Re: [PATCH 2/4] PCI: add functionality for resizing resources v3 Andy Shevchenko <andy.shevchenko@gmail.com> - 2017-04-26 19:10 +0200
      Re: [PATCH 2/4] PCI: add functionality for resizing resources v3 Christian König <deathsimple@vodafone.de> - 2017-05-02 18:00 +0200
        Re: [PATCH 2/4] PCI: add functionality for resizing resources v3 Andy Shevchenko <andy.shevchenko@gmail.com> - 2017-05-02 22:30 +0200
      Re: [PATCH 2/4] PCI: add functionality for resizing resources v3 Christian König <deathsimple@vodafone.de> - 2017-05-04 11:30 +0200
        Re: [PATCH 2/4] PCI: add functionality for resizing resources v3 Andy Shevchenko <andy.shevchenko@gmail.com> - 2017-05-04 12:20 +0200
          Re: [PATCH 2/4] PCI: add functionality for resizing resources v3 Andy Shevchenko <andy.shevchenko@gmail.com> - 2017-05-04 18:50 +0200
  [PATCH 3/4] x86/PCI: Enable a 64bit BAR on AMD Family 15h (Models 30h-3fh) Processors v2 Christian König <deathsimple@vodafone.de> - 2017-04-25 15:30 +0200
    Re: [PATCH 3/4] x86/PCI: Enable a 64bit BAR on AMD Family 15h (Models  30h-3fh) Processors v2 Alex Deucher <alexdeucher@gmail.com> - 2017-04-25 17:10 +0200
    Re: [PATCH 3/4] x86/PCI: Enable a 64bit BAR on AMD Family 15h (Models  30h-3fh) Processors v2 Andy Shevchenko <andy.shevchenko@gmail.com> - 2017-04-26 19:20 +0200
  Re: Resizeable PCI BAR support V4 Andy Shevchenko <andy.shevchenko@gmail.com> - 2017-04-25 16:30 +0200

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